 | 2010 |
|---|
| 17 |       | Andrea Pugliese,
Francesco A. Amoroso,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances.
IEEE Trans. on Circuits and Systems 57-I(3): 618-630 (2010) |
| 16 | | Andrea Pugliese,
Francesco A. Amoroso,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582].
IEEE Trans. on Circuits and Systems 57-I(7): 1812-1813 (2010) |
| 15 | | Andrea Pugliese,
Francesco A. Amoroso,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance.
Microelectronics Journal 41(7): 440-446 (2010) |
| 2009 |
|---|
| 14 | | Gregorio Cappuccino,
Francesco A. Amoroso,
Andrea Pugliese:
Class-AB output stage design for high-speed three-stage op-amps.
ICECS 2009: 1-4 |
| 13 | | Francesco A. Amoroso,
Andrea Pugliese,
Gregorio Cappuccino:
Design considerations for fast-settling two-stage Miller-compensated operational amplifiers.
ICECS 2009: 5-8 |
| 12 | | Andrea Pugliese,
Francesco A. Amoroso,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.
ISCAS 2009: 3134-3137 |
| 11 | | Andrea Pugliese,
Francesco A. Amoroso,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies.
IEEE Trans. on Circuits and Systems 56-I(12): 2569-2582 (2009) |
| 2008 |
|---|
| 10 | | Andrea Pugliese,
Francesco A. Amoroso,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
PATMOS 2008: 318-327 |
| 9 | | Andrea Pugliese,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers.
IEEE Trans. on Circuits and Systems 55-II(1): 1-5 (2008) |
| 2007 |
|---|
| 8 | | Andrea Pugliese,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Settling Time Minimization of Operational Amplifiers.
PATMOS 2007: 107-116 |
| 2006 |
|---|
| 7 | | Andrea Pugliese,
Gregorio Cappuccino,
Giuseppe Cocorullo:
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
PATMOS 2006: 311-318 |
| 6 | | Andrea Pugliese,
Gregorio Cappuccino,
Giuseppe Cocorullo:
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.
PATMOS 2006: 524-531 |
| 2005 |
|---|
| 5 | | Gregorio Cappuccino,
Andrea Pugliese,
Giuseppe Cocorullo:
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
PATMOS 2005: 329-336 |
| 2003 |
|---|
| 4 | | Gregorio Cappuccino:
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects.
DSD 2003: 138-143 |
| 2002 |
|---|
| 3 | | Gregorio Cappuccino,
Giuseppe Cocorullo:
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
PATMOS 2002: 438-447 |
| 2001 |
|---|
| 2 | | Gregorio Cappuccino,
Giuseppe Cocorullo:
CMOS sizing rule for high performance long interconnects.
DATE 2001: 817 |
| 1999 |
|---|
| 1 | | Gregorio Cappuccino,
Giuseppe Cocorullo:
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
EUROMICRO 1999: 1204-1208 |
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