Ke Cao

	2007
3		Ke Cao, Jiang Hu, Mosong Cheng: Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. VLSI Syst. 15(12): 1332-1340 (2007)
	2006
2		Ke Cao, Sorin Dobre, Jiang Hu: Standard cell characterization considering lithography induced variations. DAC 2006: 801-804
	2005
1		Ke Cao, Puneet Dhawan, Jiang Hu: Library cell layout with Alt-PSM compliance and composability. ASP-DAC 2005: 216-219

Coauthor Index

1	Mosong Cheng	[3]
2	Puneet Dhawan	[1]
3	Sorin Dobre	[2]
4	Jiang Hu	[1] [2] [3]

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page