 | 2011 |
| 23 |  | Nivard Aymerich,
Shrikanth Ganapathy,
Antonio Rubio,
Ramon Canal,
Antonio González:
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells.
ACM Great Lakes Symposium on VLSI 2011: 277-282 |
| 22 |  | Shrikanth Ganapathy,
Ramon Canal,
Antonio González,
Antonio Rubio:
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors.
ICCD 2011: 332-338 |
| 21 |  | Nivard Aymerich,
A. Asenov,
A. Brown,
Ramon Canal,
B. Cheng,
Joan Figueras,
Antonio González,
Enric Herrero,
S. Markov,
Miguel Miranda,
P. Pouyan,
Tanausu Ramirez,
Antonio Rubio,
I. Vatajelu,
Xavier Vera,
X. Wang,
Paul Zuber:
New reliability mechanisms in memory design for sub-22nm technologies.
IOLTS 2011: 111-114 |
| 2010 |
| 20 |  | Shrikanth Ganapathy,
Ramon Canal,
Antonio González,
Antonio Rubio:
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability.
DATE 2010: 417-422 |
| 19 |  | Enric Herrero,
José González,
Ramon Canal:
Power-Efficient Spilling Techniques for Chip Multiprocessors.
Euro-Par (1) 2010: 256-267 |
| 18 |  | Enric Herrero,
José González,
Ramon Canal:
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors.
ISCA 2010: 419-428 |
| 17 |  | Shrikanth Ganapathy,
Ramon Canal,
Antonio González,
Antonio Rubio:
MODEST: a model for energy estimation under spatio-temporal variability.
ISLPED 2010: 129-134 |
| 2009 |
| 16 |  | Matteo Monchiero,
Ramon Canal,
Antonio González:
Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs.
ICPP 2009: 1-8 |
| 15 |  | Alejandro Valero,
Julio Sahuquillo,
Salvador Petit,
Vicente Lorente,
Ramon Canal,
Pedro López,
José Duato:
An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
MICRO 2009: 213-221 |
| 2008 |
| 14 |  | Enric Herrero,
José González,
Ramon Canal:
Distributed cooperative caching.
PACT 2008: 134-143 |
| 13 |  | Xiaoyao Liang,
Ramon Canal,
Gu-Yeon Wei,
David Brooks:
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
IEEE Micro 28(1): 60-68 (2008) |
| 12 |  | Matteo Monchiero,
Ramon Canal,
Antonio González:
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures.
IEEE Trans. Parallel Distrib. Syst. 19(5): 666-681 (2008) |
| 2007 |
| 11 |  | Xiaoyao Liang,
Ramon Canal,
Gu-Yeon Wei,
David Brooks:
Process Variation Tolerant 3T1D-Based Cache Architectures.
MICRO 2007: 15-26 |
| 2006 |
| 10 |  | Matteo Monchiero,
Ramon Canal,
Antonio González:
Design space exploration for multicore architectures: a power/performance/thermal view.
ICS 2006: 177-186 |
| 2005 |
| 9 |  | Ramon Canal,
Antonio González,
James E. Smith:
Value Compression for Efficient Computation.
Euro-Par 2005: 519-529 |
| 2004 |
| 8 |  | Ramon Canal,
Antonio González,
James E. Smith:
Software-Controlled Operand-Gating.
CGO 2004: 125-136 |
| 2003 |
| 7 |  | Jaume Abella,
Ramon Canal,
Antonio González:
Power- and Complexity-Aware Issue Queue Designs.
IEEE Micro 23(5): 50-58 (2003) |
| 2001 |
| 6 |  | Ramon Canal,
Antonio González:
Reducing the complexity of the issue logic.
ICS 2001: 312-320 |
| 5 |  | Ramon Canal,
Joan-Manuel Parcerisa,
Antonio González:
Dynamic Code Partitioning for Clustered Architectures.
International Journal of Parallel Programming 29(1): 59-79 (2001) |
| 2000 |
| 4 |  | Ramon Canal,
Joan-Manuel Parcerisa,
Antonio González:
Dynamic Cluster Assignment Mechanisms.
HPCA 2000: 133-142 |
| 3 |  | Ramon Canal,
Antonio González:
A low-complexity issue logic.
ICS 2000: 327-335 |
| 2 |  | Ramon Canal,
Antonio González,
James E. Smith:
Very low power pipelines using significance compression.
MICRO 2000: 181-190 |
| 1999 |
| 1 |  | Ramon Canal,
Joan-Manuel Parcerisa,
Antonio González:
A Cost-Effective Clustered Architecture.
IEEE PACT 1999: 160-168 |