Andrea Calimera

	2012
33		Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino: NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI 2012: 279-282
32		Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Rich Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo: Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. DATE 2012: 165-166
31		Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino: IR-drop analysis of graphene-based power distribution networks. DATE 2012: 81-86
30		Andrea Calimera, Enrico Macii, Massimo Poncino: Design Techniques for NBTI-Tolerant Power-Gating Architectures. IEEE Trans. on Circuits and Systems 59-II(4): 249-253 (2012)
	2011
29		Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino: Buffering of frequent accesses for reduced cache aging. ACM Great Lakes Symposium on VLSI 2011: 295-300
28		Salvatore Rinaudo, Giuliana Gangemi, Andrea Calimera, Alberto Macii, Massimo Poncino: Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. DATE 2011: 1127-1128
27		Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino: Partitioned cache architectures for reduced NBTI-induced aging. DATE 2011: 938-943
26		Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. PATMOS 2011: 162-172
25		Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. PATMOS 2011: 214-225
	2010
24		Andrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella: An integrated thermal estimation framework for industrial embedded platforms. ACM Great Lakes Symposium on VLSI 2010: 293-298
23		Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino: Aging effects of leakage optimizations for caches. ACM Great Lakes Symposium on VLSI 2010: 95-98
22		Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino: Post-placement temperature reduction techniques. DATE 2010: 634-637
21		Andrea Calimera, Enrico Macii, Massimo Poncino: Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. ISCAS 2010: 785-788
20		Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino: Dynamic indexing: concurrent leakage and aging optimization for caches. ISLPED 2010: 343-348
19		Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda: Generating power-hungry test programs for power-aware validation of pipelined processors. SBCCI 2010: 61-66
18		Andrea Calimera, Enrico Macii, Massimo Poncino: NBTI-Aware Clustered Power Gating. ACM Trans. Design Autom. Electr. Syst. 16(1): 3 (2010)
17		Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. IEEE Trans. VLSI Syst. 18(11): 1608-1620 (2010)
16		Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Dual-Vt assignment policies in ITD-aware synthesis. Microelectronics Journal 41(9): 547-553 (2010)
	2009
15		Andrea Calimera, Enrico Macii, Massimo Poncino: NBTI-aware sleep transistor design for reliable power-gating. ACM Great Lakes Symposium on VLSI 2009: 333-338
14		Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: Enabling concurrent clock and power gating in an industrial design flow. DATE 2009: 334-339
13		Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: Placement-aware Clustering for Integrated Clock and Power Gating. ISCAS 2009: 1723-1726
12		Andrea Calimera, Enrico Macii, Massimo Poncino: NBTI-aware power gating for concurrent leakage and aging optimization. ISLPED 2009: 127-132
11		Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. PATMOS 2009: 227-236
10		Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino: On-chip Thermal Modeling Based on SPICE Simulation. PATMOS 2009: 66-75
9		Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. IEEE Trans. on Circuits and Systems 56-I(9): 1979-1993 (2009)
	2008
8		Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar: Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI 2008: 5-10
7		Andrea Calimera, Luca Benini, Enrico Macii: Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. DATE 2008: 973-978
6		Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino: Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. DSD 2008: 298-303
5		Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764
4		Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino: Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED 2008: 217-220
3		Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino: Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electronics 4(3): 374-384 (2008)
	2007
2		Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504
1		Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE 2007: 1544-1549

Coauthor Index

1	Andrea Acquaviva	[24]
2	Eduard Babayan	[32]
3	R. Iris Bahar	[3] [4] [8] [16] [17]
4	Luca Benini	[1] [2] [5] [7] [9]
5	Leticia Maria Veiras Bolzani (Leticia Maria Veiras Bolzani Poehls)	[6] [13] [14]
6	Karthik Duraisami	[3]
7	Giuliana Gangemi	[28]
8	Matteo Giaconia	[24]
9	Rich Goldman	[32]
10	Hossein Karimiyan	[26]
11	Karthikeyan Lingasubramanian	[25]
12	Wei Liu	[10] [22] [33]
13	Mirko Loghi	[20] [23] [27] [29]
14	Alberto Macii	[1] [2] [3] [5] [6] [9] [11] [13] [14] [24] [25] [26] [28] [32]
15	Enrico Macii	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [29] [30] [31] [32] [33]
16	Vazgen Melikyan	[32]
17	Sandeep Miryala	[31] [33]
18	Alberto Nannarelli	[10] [22]
19	Claudio Parrella	[24]
20	Massimo Poncino	[1] [2] [3] [4] [5] [6] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33]
21	Antonio Pullini	[2] [5]
22	Danilo Ravotto	[19]
23	Matteo Sonza Reorda	[19]
24	Salvatore Rinaudo	[28] [32]
25	Ernesto Sánchez (Edgar E. Sánchez, Edgar Ernesto Sánchez Sánchez)	[19]
26	Alessandro Sassone	[32]
27	Ashoka Visweswara Sathanur	[1] [2] [3] [5]
28	Prassanna Sithambaram	[3]
29	Valerio Tenace	[33]
30	Gaurang Upasani	[11]

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