Ney Laert Vilar Calazans

Ney Calazans

	2012
57		Julian J. H. Pontes, Ney Calazans, Pascal Vivet: An accurate Single Event Effect digital design flow for reliable system level design. DATE 2012: 224-229
56		Matheus T. Moreira, Bruno Cruz de Oliveira, Fernando Moraes, Ney Calazans: Impact of C-elements in asynchronous circuits. ISQED 2012: 437-343
55		Taciano Perez, Ney Laert Vilar Calazans, César A. F. De Rose: A preliminary study on system-level impact of persistent main memory. ISQED 2012: 84-90
	2011
54		Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans: Adapting a C-element design flow for low power. ICECS 2011: 45-48
53		Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Arbitration and routing impact on NoC design. International Symposium on Rapid System Prototyping 2011: 193-198
52		Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans: A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC 2011: 99-104
51		Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres: A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. IEEE Design & Test of Computers 28(5): 62-71 (2011)
50		César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin: CAFES: A framework for intrachip application modeling and communication architecture design. J. Parallel Distrib. Comput. 71(5): 714-728 (2011)
	2010
49		Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans: Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS 2010: 150-159
48		Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres: A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. SBCCI 2010: 115-120
47		Leonel Tedesco, Thiago R. da Rosa, Fabien Clermidy, Ney Calazans, Fernando Gehm Moraes: Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip. SBCCI 2010: 91-96
46		Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans: Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC 2010: 493-498
45		Ewerson Luiz de Souza Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Dynamic Task Mapping for MPSoCs. IEEE Design & Test of Computers 27(5): 26-35 (2010)
	2009
44		Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Evaluation on FPGA of triple rail logic robustness against DPA and DEMA. DATE 2009: 634-639
43		Everton Carara, Roberto P. de Oliveira, Ney Laert Vilar Calazans, Fernando Gehm Moraes: HeMPS - a Framework for NoC-based MPSoC Generation. ISCAS 2009: 1345-1348
42		Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. ReConFig 2009: 24-29
41		Guilherme Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes: A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. ReConFig 2009: 30-35
	2008
40		Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya: Integrating Abstract NoC Models within MPSoC Design. IEEE International Workshop on Rapid System Prototyping 2008: 65-71
39		Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans: Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI 2008: 347-352
38		Guilherme Guindani, Cezar Reinbrecht, Thiago Raupp, Ney Calazans, Fernando Gehm Moraes: NoC Power Estimation at the RTL Abstraction Level. ISVLSI 2008: 475-478
37		Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans: Triple Rail Logic Robustness against DPA. ReConFig 2008: 415-420
36		Fernando Gehm Moraes, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans: MOTIM: an industrial application using nocs. SBCCI 2008: 182-187
35		Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert: Evaluating the robustness of secure triple track logic through prototyping. SBCCI 2008: 193-198
34		César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Computers & Digital Techniques 2(6): 471-482 (2008)
	2007
33		Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans: SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD 2007: 541-546
32		Luis Carlos Caruso, Guilherme Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes: SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. IEEE International Workshop on Rapid System Prototyping 2007: 27-33
31		Ewerson Carvalho, Ney Calazans, Fernando Moraes: Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. IEEE International Workshop on Rapid System Prototyping 2007: 34-40
30		César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Evaluation of Algorithms for Low Energy Mapping onto NoCs. ISCAS 2007: 389-392
29		Erico Bastos, Everton Carara, Daniel V. Pigatto, Ney Laert Vilar Calazans, Fernando Moraes: MOTIM - A Scalable Architecture for Ethernet Switches. ISVLSI 2007: 451-452
28		Ewerson Carvalho, Ney Laert Vilar Calazans, Fernando Gehm Moraes: Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload. ISVLSI 2007: 459-460
27		Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes: A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. ReCoSoC 2007: 23-30
26		Everton Carara, Fernando Moraes, Ney Calazans: Router architecture for high-performance NoCs. SBCCI 2007: 111-116
25		Leonel Tedesco, Fernando Moraes, Ney Calazans: Buffer sizing for QoS flows in wormhole packet switching NoCs. SBCCI 2007: 99-104
24		Aline Mello, Ney Laert Vilar Calazans: Rate-based scheduling policy for QoS flows in networks on chip. VLSI-SoC 2007: 140-145
23		César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique CoRR abs/0710.4738: (2007)
22		Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes: MultiNoC: A Multiprocessing System Enabled by a Network on Chip CoRR abs/0710.4843: (2007)
	2006
21		Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes: Reconfigurable Systems Enabled by a Network-on-Chip. FPL 2006: 1-4
20		Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes: Infrastructure for dynamic reconfigurable systems: choices and trade-offs. SBCCI 2006: 44-49
19		Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes: Application driven traffic modeling for NoCs. SBCCI 2006: 62-67
	2005
18		Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes, Ney Calazans: MAIA: a framework for networks on chip generation and verification. ASP-DAC 2005: 49-52
17		César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel: Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. DATE 2005: 502-507
16		César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans: Models for Embedded Application Mapping onto NoCs: Timing Analysis. IEEE International Workshop on Rapid System Prototyping 2005: 17-23
15		Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans: Energy and latency evaluation of NoC topologies. ISCAS (6) 2005: 5866-5869
14		Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes: Virtual channels in networks on chip: implementation and evaluation on hermes NoC. SBCCI 2005: 178-183
13		Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes: Traffic generation and performance evaluation for mesh-based NoCs. SBCCI 2005: 184-189
12		José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin: Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. SBCCI 2005: 196-201
11		César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis: Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. VLSI-SoC 2005: 179-194
	2004
10		Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes: MultiNoC: A Multiprocessing System Enabled by a Network on Chip. DATE 2004: 234-239
9		Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato: FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. FPL 2004: 1042-1046
8		Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes: PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. SBCCI 2004: 10-15
7		Fernando Gehm Moraes, Ney Calazans, Aline Mello, Leandro Möller, Luciano Ost: HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integration 38(1): 69-93 (2004)
	2003
6		Fernando Gehm Moraes, Daniel Mesquita, José Carlos S. Palma, Leandro Möller, Ney Laert Vilar Calazans: Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs. DATE 2003: 11122-11123
5		Daniel Mesquita, Fernando Gehm Moraes, José Palma, Leandro Möller, Ney Laert Vilar Calazans: Remote and Partial Reconfiguration of FPGAs: Tools and Trends. IPDPS 2003: 177
4		Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara: From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. SBCCI 2003: 355-
3		Fernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans: A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping. VLSI-SOC 2003: 318-323
	2001
2		Ney Laert Vilar Calazans, Fernando Gehm Moraes, Delfim Luiz Torok, Andrey V. Andreoli: Projeto para Prototipação de um IP Soft Core MAC Ethernet. RITA 8(1): 23-41 (2001)
	1994
1		Ney Laert Vilar Calazans: Boolean constrained encoding: a new formulation and a case study. ICCAD 1994: 702-706

Coauthor Index

1	Andrey V. Andreoli	[2]
2	Erico Bastos	[29]
3	Eduardo Wenzel Brião	[8] [9]
4	Daniel Camozzato	[9]
5	Everton Carara (Everton Alceu Carara)	[4] [26] [29] [36] [43]
6	Luigi Carro	[15]
7	Luis Carlos Caruso	[32]
8	Ewerson Carvalho (Ewerson Luiz de Souza Carvalho)	[8] [9] [20] [27] [28] [31] [33] [45]
9	Fabien Clermidy	[47]
10	Amine Dehbaoui	[48]
11	Frederico Ferlini	[41]
12	Diego Garibotti	[13]
13	Leonardo Giacomet	[19]
14	Ismael Grehs	[20] [21] [27]
15	Guilherme Guindani	[32] [38] [41]
16	Fabiano Hessel	[4] [17] [23] [50]
17	Ahmed Amine Jerraya	[40]
18	Márcio Eduardo Kreutz	[15] [16]
19	Victor Lomné	[35] [37] [44] [48]
20	César A. M. Marcon (César Augusto Missio Marcon)	[11] [12] [15] [16] [17] [23] [30] [34] [50] [53]
21	Philippe Maurine	[35] [37] [44] [48] [51]
22	Aline Mello	[3] [7] [10] [13] [14] [18] [19] [22] [24]
23	Daniel Mesquita	[5] [6]
24	Leandro Möller	[3] [5] [6] [7] [9] [10] [20] [21] [22] [27]
25	Fernando Gehm Moraes (Fernando Moraes)	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [17] [18] [19] [20] [21] [22] [23] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [36] [38] [41] [42] [43] [45] [46] [47] [49] [50] [51] [53] [54] [56]
26	Matheus T. Moreira	[39] [46] [49] [52] [54] [56]
27	Edson I. Moreno (Edson Ifarraguirre Moreno)	[4] [30] [34] [40] [50] [53]
28	Bruno Cruz de Oliveira	[52] [54] [56]
29	Jeferson Oliveira	[41]
30	Roberto P. de Oliveira	[43]
31	Thomas Ordas	[37]
32	Luciano Ost	[3] [7] [18]
33	José Palma	[5] [18]
34	José Carlos S. Palma	[6] [11] [12]
35	Taciano Perez	[55]
36	Daniel V. Pigatto	[29] [36] [41]
37	Julian J. H. Pontes	[33] [39] [46] [49] [52] [54] [57]
38	Katalin Popovici (Katalin Maria Popovici)	[40]
39	Thiago Raupp	[38]
40	Cezar Reinbrecht	[38]
41	Igor M. Reis	[17] [23]
42	Ricardo Augusto da Luz Reis (Ricardo A. L. Reis, Ricardo Reis)	[11] [12]
43	Michel Robert	[35] [37] [44]
44	Taciano A. Rodolfo	[42]
45	Thiago R. da Rosa	[47]
46	Vitor M. da Rosa	[4]
47	César A. F. De Rose (César Augusto Fonticielha De Rose)	[55]
48	Hugo Schmitt	[32]
49	Rafael Soares (Rafael Iankowski Soares)	[20] [27] [33] [35] [37] [39] [44] [48] [51]
50	Altamiro Amadeu Susin	[11] [12] [15] [16] [17] [23] [50]
51	Leonel Tedesco	[13] [14] [19] [25] [47]
52	Delfim Luiz Torok	[2]
53	Lionel Torres	[35] [37] [44] [48] [51]
54	Pascal Vivet	[57]

Colors in the list of coauthors

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