Jean Paul Caisso

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1991

2 Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin: A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 589-595 (1991)

1988

1 Jean Paul Caisso, Bernard Courtois: Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level. ITC 1988: 94-101

	1991
2		Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin: A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 589-595 (1991)
	1988
1		Jean Paul Caisso, Bernard Courtois: Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level. ITC 1988: 94-101

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