Michael L. Bushnell

	2009
91		Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. VLSI Syst. 17(10): 1534-1545 (2009)
	2008
90		Hari Vijay Venkatanarayanan, Michael L. Bushnell: A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. VLSI Design 2008: 581-588
89		Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal: Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS 2008: 329-335
	2007
88		Baozhen Yu, Michael L. Bushnell: Power Grid Analysis of Dynamic Power Cutoff Technology. ISCAS 2007: 1393-1396
87		Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal: SPARTAN: a spectral and information theoretic approach to partial-scan. ITC 2007: 1-10
86		Rohit Pandey, Michael L. Bushnell: Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. VLSI Design 2007: 121-126
85		Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell: Zero Cost Test Point Insertion Technique for Structured ASICs. VLSI Design 2007: 357-363
84		Suresh Kumar Devanathan, Michael L. Bushnell: Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. VLSI Design 2007: 485-491
83		Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie: Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. VLSI Design 2007: 657-664
82		Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell: A Neural Net Branch Predictor to Reduce Power. VLSI Design 2007: 679-684
81		Jeffrey Ayres, Michael L. Bushnell: Analog Circuit Testing Using Auto Regressive Moving Average Models. VLSI Design 2007: 775-780
80		Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal: Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. IEEE Trans. VLSI Syst. 15(11): 1245-1255 (2007)
	2006
79		Baozhen Yu, Michael L. Bushnell: A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. ISLPED 2006: 214-219
78		Hari Vijay Venkatanarayanan, Michael L. Bushnell: An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. VLSI Design 2006: 161-168
77		Suresh Kumar Devanathan, Michael L. Bushnell: Sequential Spectral ATPG Using the Wavelet Transform and Compaction. VLSI Design 2006: 407-412
76		Shweta Chary, Michael L. Bushnell: Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 413-418
75		Omar I. Khan, Michael L. Bushnell: Aliasing Analysis of Spectral Statistical Response Compaction Techniques. VLSI Design 2006: 801-806
74		Shweta Chary, Michael L. Bushnell: Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. VLSI Design 2006: 818-823
73		Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electronics 2(1): 121-128 (2006)
	2005
72		Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS 2005: 436-445
71		Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Variable Input Delay CMOS Logic for Low Power Design. VLSI Design 2005: 598-605
70		Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell: Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. VLSI Design 2005: 723-729
	2004
69		Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal: On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. ITC 2004: 617-626
68		Omar I. Khan, Michael L. Bushnell: Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. ITC 2004: 67-76
67		Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design 2004: 1035-1040
66		Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: A Tuturial on the Emerging Nanotechnology Devices. VLSI Design 2004: 343-360
65		Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell: A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. J. Comput. Sci. Technol. 19(6): 955-964 (2004)
	2003
64		Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell: A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. VLSI Design 2003: 149-154
63		Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal: New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. VLSI Design 2003: 353-360
62		Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design 2003: 527-532
	2002
61		Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell: A New Transitive Closure Algorithm with Application to Redundancy Identification. DELTA 2002: 496-500
60		Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal: Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ITC 2002: 375-383
59		Vishwani D. Agrawal, Michael L. Bushnell: Electronic Testing for SOC Designers (Tutorial Abstract). VLSI Design 2002: 20
	2001
58		Sanjay Mohan, Michael L. Bushnell: A Code Transition Delay Model for ADC Test. VLSI Design 2001: 274-282
	2000
57		Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 8(2): 223-228 (2000)
56		Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Improving path delay testability of sequential circuits. IEEE Trans. VLSI Syst. 8(6): 736-741 (2000)
55		Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi: False-Path Removal Using Delay Fault Simulation. J. Electronic Testing 16(5): 463-476 (2000)
	1999
54		Michael L. Bushnell: Increasing Test Coverage in a VLSI Design Course. ITC 1999: 1133
53		Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss: Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design 1999: 434-439
52		Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell: A Complete Characterization of Path Delay Faults through Stuck-at Faults. VLSI Design 1999: 492-497
51		Rajesh Ramadoss, Michael L. Bushnell: Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. J. Electronic Testing 14(3): 189-205 (1999)
50		Madhu K. Iyer, Michael L. Bushnell: Effect of Noise on Analog Circuit Testing. J. Electronic Testing 15(1-2): 11-22 (1999)
	1998
49		Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell: False-Path Removal Using Delay Fault Simulation. Asian Test Symposium 1998: 82-87
48		Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu: A non-enumerative path delay fault simulator for sequential circuits. ITC 1998: 934-943
47		Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal: Path Delay Testing: Variable-Clock Versus Rated-Clock. VLSI Design 1998: 470-475
46		Madhu K. Iyer, Michael L. Bushnell: Effect of Noise on Analog Circuit Testing. VTS 1998: 138-144
45		Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell: On Delay-Untestable Paths and Stuck-Fault Redundancy. VTS 1998: 194-199
44		Ganapathy Parthasarathy, Michael L. Bushnell: Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. VTS 1998: 210-217
43		Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: The path-status graph with application to delay fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 324-332 (1998)
42		Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 873-876 (1998)
41		Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas: Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. J. Electronic Testing 12(3): 239-254 (1998)
	1997
40		Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal: Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. VLSI Design 1997: 88-94
39		Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: On variable clock methods for path delay testing of sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1237-1249 (1997)
38		Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel: Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 759-762 (1997)
37		Michael L. Bushnell, John Giraldi: A Functional Decomposition Method for Redundancy Identification and Test Generation. J. Electronic Testing 10(3): 175-195 (1997)
36		Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. J. Electronic Testing 11(1): 55-67 (1997)
	1996
35		Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin: Redundancy Identification Using Transitive Closure. Asian Test Symposium 1996: 4-9
34		Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. ITC 1996: 276-285
33		Rajesh Ramadoss, Michael L. Bushnell: Test generation for mixed-signal devices using signal flow graphs. VLSI Design 1996: 242-248
32		Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas: Statistical path delay fault coverage estimation for synchronous sequential circuits. VLSI Design 1996: 290-295
31		Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Parallel concurrent path-delay fault simulation using single-input change patterns. VLSI Design 1996: 426-431
30		Xinghao Chen, Michael L. Bushnell: Sequential circuit test generation using dynamic justification equivalence. J. Electronic Testing 8(1): 9-33 (1996)
	1995
29		Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell: Functional test generation for path delay faults. Asian Test Symposium 1995: 339-345
28		James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal: An adaptive distributed algorithm for sequential circuit test generation. EURO-DAC 1995: 236-241
27		Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. ITC 1995: 139-148
26		Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell: Statistical methods for delay fault coverage analysis. VLSI Design 1995: 166-170
25		Imtiaz P. Shaik, Michael L. Bushnell: A graph approach to DFT hardware placement for robust delay fault BIST. VLSI Design 1995: 177-182
24		James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal: An asynchronous algorithm for sequential circuit test generation on a network of workstations. VLSI Design 1995: 36-41
23		Xinghao Chen, Michael L. Bushnell: Generation of search state equivalence for automatic test pattern generation. VLSI Design 1995: 99-103
22		Imtiaz P. Shaik, Michael L. Bushnell: Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . VTS 1995: 393-399
21		Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell: Fault coverage estimation by test vector sampling. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 590-596 (1995)
	1994
20		Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal: An Efficient Path Delay Fault Coverage Estimator. DAC 1994: 516-521
19		Sandip Parikh, David Sarnoff, Michael L. Bushnell, James Sienicki, Ramakrishnan Ganesh: Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. EDAC-ETC-EUROASIC 1994: 610-617
18		Xinghao Chen, Michael L. Bushnell: Dynamic State and Objective Learning for Sequential Circuit Automatic Test Generation Using Decomposition Equivalence. FTCS 1994: 446-455
17		James Sienicki, Michael L. Bushnell, Sandip Parikh: Graphical Methodology Language for CAD Frameworks. VLSI Design 1994: 401-406
16		Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Energy minimization and design for testability. J. Electronic Testing 5(1): 57-66 (1994)
	1993
15		Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Design for Testability for Path Delay faults in Sequential Circuits. DAC 1993: 453-457
	1992
14		Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC 1992: 165-172
13		Srimat T. Chakradhar, Michael L. Bushnell: A solvable class of quadratic 0-1 programming. Discrete Applied Mathematics 36(3): 233-251 (1992)
	1991
12		John Giraldi, Michael L. Bushnell: Search State Equivalence for Redundancy Identification and Test Generation. ITC 1991: 184-193
	1990
11		Daniel R. Brasen, Michael L. Bushnell: MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. DAC 1990: 107-110
10		Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Automatic Test Generation Using Quadratic 0-1 Programming. DAC 1990: 654-659
9		John Giraldi, Michael L. Bushnell: EST: The New Frontier in Automatic Test-Pattern Generation. DAC 1990: 667-672
8		Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Polynomial time solvable fault detection problems. FTCS 1990: 56-63
7		Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong: Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Design & Test of Computers 7(5): 54-57 (1990)
6		Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal: Toward massively parallel automatic test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 981-994 (1990)
	1989
5		Michael L. Bushnell, Stephen W. Director: Automated design tool execution in the Ulysses design environment. IEEE Trans. on CAD of Integrated Circuits and Systems 8(3): 279-287 (1989)
	1988
4		Xinghao Chen, Michael L. Bushnell: A Module Area Estimator for VLSI Layout. DAC 1988: 54-59
	1987
3		Michael L. Bushnell, Stephen W. Director: ULYSSES - a knowledge-based VLSI design environment. AI in Engineering 2(1): 33-41 (1987)
	1986
2		Michael L. Bushnell, Stephen W. Director: VLSI CAD tool integration using the Ulysses environment. DAC 1986: 55-61
1		Michael L. Bushnell, Pierre Haren: Guest editorial. AI in Engineering 1(2): 67-69 (1986)

Coauthor Index

1	Prathima Agrawal	[24] [28]
2	Vishwani D. Agrawal	[6] [7] [8] [10] [14] [15] [16] [20] [21] [24] [26] [27] [28] [29] [31] [32] [34] [35] [36] [38] [39] [40] [41] [42] [43] [45] [47] [48] [49] [52] [53] [55] [56] [57] [59] [60] [61] [62] [63] [64] [65] [66] [67] [69] [70] [71] [72] [73] [80] [87] [89] [91]
3	Jeffrey Ayres	[81]
4	Bhargab B. Bhattacharya	[52] [65]
5	Richard J. Blaikie	[83]
6	Daniel R. Brasen	[11]
7	Tapan J. Chakraborty	[14] [15] [39] [56] [57]
8	Srimat T. Chakradhar	[6] [7] [8] [10] [13] [16] [85]
9	Shweta Chary	[74] [76]
10	Xinghao Chen	[4] [18] [23] [30]
11	Kunal K. Dave	[64] [70]
12	Suresh Kumar Devanathan	[77] [84] [87]
13	Stephen W. Director	[2] [3] [5]
14	Ramakrishnan Ganesh	[19]
15	Vivek Gaur	[61]
16	Marwan A. Gharaybeh	[27] [31] [34] [36] [42] [43] [49] [55]
17	John Giraldi	[9] [12] [37]
18	Pierre Haren	[1]
19	Keerthi Heragu	[20] [21] [26] [38]
20	Madhu K. Iyer	[46] [50]
21	Omar I. Khan	[68] [75] [82] [87]
22	Qing Lin	[35]
23	Subhashis Majumder	[45] [47] [52] [65]
24	Daniel Mazor	[83]
25	Vishal J. Mehta	[64]
26	Sanjay Mohan	[58]
27	David J. Mulligan	[83]
28	Rohit Pandey	[86]
29	Lakshminarayana Pappu	[32] [41]
30	Sandip Parikh	[17] [19]
31	Carlos G. Parodi	[48] [55]
32	Ganapathy Parthasarathy	[44] [53]
33	Janak H. Patel	[38]
34	Tezaswi Raja	[62] [66] [67] [71] [72] [73] [91]
35	Rajesh Ramadoss	[33] [51] [53]
36	Lan Rao	[63] [80]
37	David Sarnoff	[19]
38	Aditya D. Sathe	[60]
39	Rajamani Sethuram	[82] [85] [89]
40	Imtiaz P. Shaik	[22] [25]
41	James Sienicki	[17] [19] [24] [28]
42	Mandyam-Komar Srinivas	[29] [32] [40] [41]
43	Thomas K. Truong	[7]
44	Hari Vijay Venkatanarayanan	[78] [82] [90]
45	Seongmoon Wang	[85]
46	Shianling Wu	[48]
47	Baozhen Yu	[79] [88]
48	Junwu Zhang	[69]

Colors in the list of coauthors

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