Sanad Bushnaq

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2011

2 Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada: All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS 2011: 607-610

2009

1 Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209

	2011
2		Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada: All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS 2011: 607-610
	2009
1		Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209

Coauthor Index

1 Kunihiro Asada [1] [2]

2 Makoto Ikeda [1] [2]

3 Toru Nakura [1]

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team —

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