 | 2012 |
| 11 |  | Kieran McLaughlin,
Dwayne Burns,
Ciaran Toal,
Colm McKillen,
Sakir Sezer:
Fully hardware based WFQ architecture for high-speed QoS packet scheduling.
Integration 45(1): 99-109 (2012) |
| 2011 |
| 10 |  | Antonio Munoz,
Sakir Sezer,
Dwayne Burns,
Gareth Douglas:
An Approach for Unifying Rule Based Deep Packet Inspection.
ICC 2011: 1-5 |
| 9 |  | Thianantha Arumugam,
Sakir Sezer,
Dwayne Burns,
Vishalini Vasu:
High performance multi-engine regular expression processing.
SoCC 2011: 347-352 |
| 2010 |
| 8 |  | Xin Yang,
Sakir Sezer,
John V. McCanny,
Dwayne Burns:
High-Performance random data lookup for network processing.
SoCC 2010: 272-277 |
| 2009 |
| 7 |  | Xin Yang,
Sakir Sezer,
John V. McCanny,
Dwayne Burns:
DDR3 based lookup circuit for high-performance network processing.
SoCC 2009: 351-354 |
| 2007 |
| 6 |  | Ciaran Toal,
Dwayne Burns,
Kieran McLaughlin,
Sakir Sezer,
Stephen O'Kane:
An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing.
AHS 2007: 613-618 |
| 5 |  | Xin Yang,
Sakir Sezer,
John V. McCanny,
Dwayne Burns:
Novel Content Addressable Memory Architecture for Adaptive Systems.
AHS 2007: 633-640 |
| 4 |  | Dwayne Burns,
Ciaran Toal,
Kieran McLaughlin,
Sakir Sezer,
Mike Hutton,
Kevin Cackovic:
An FPGA Based Memory Efficient Shared Buffer Implementation.
FPL 2007: 661-664 |
| 3 |  | Ciaran Toal,
Sakir Sezer,
Xin Yang,
Kieran McLaughlin,
Dwayne Burns,
Tiberiu Seceleanu:
Programmable CRC circuit architecture.
SoCC 2007: 123-126 |
| 2 |  | Xin Yang,
Sakir Sezer,
John V. McCanny,
Dwayne Burns:
A versatile content addressable memory architecture.
SoCC 2007: 215-218 |
| 1 |  | Jun Mu,
Sakir Sezer,
Gareth Douglas,
Dwayne Burns,
Emi Garcia,
Mike Hutton,
Kevin Cackovic:
Accelerating pattern matching for DPI.
SoCC 2007: 83-86 |