 | 2011 |
| 11 |  | Michel Voyer,
Sylvain-Robert Rivard,
Luc Morin,
Hung Tien Bui:
Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction.
ISCAS 2011: 85-88 |
| 2010 |
| 10 |  | Jogendra Singh Thongam,
Pierre Bouchard,
Valentin Giurgiu,
Hung Tien Bui,
Mohand Ouhrouche:
Sensorless vector control of PMSG for variable speed wind energy applications.
CCECE 2010: 1-5 |
| 9 |  | Marcel Siadjine Njinowa,
Hung Tien Bui,
François R. Boyer:
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS).
ISCAS 2010: 1312-1315 |
| 2008 |
| 8 |  | Hung Tien Bui:
Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis.
ISCAS 2008: 3422-3425 |
| 7 |  | Hung Tien Bui,
Yvon Savaria:
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop.
IEEE Trans. on Circuits and Systems 55-I(3): 766-774 (2008) |
| 2007 |
| 6 |  | Bill Pontikakis,
Hung Tien Bui,
François R. Boyer,
Yvon Savaria:
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.
ISCAS 2007: 633-636 |
| 2006 |
| 5 |  | Hung Tien Bui,
Yvon Savaria:
High speed differential pulse-width control loop based on frequency-to-voltage converters.
ACM Great Lakes Symposium on VLSI 2006: 53-56 |
| 4 |  | Hung Tien Bui:
Dual-Path and Diode-Tracking Active Inductors for MCML Gates.
CCECE 2006: 1060-1063 |
| 2005 |
| 3 |  | Hung Tien Bui,
Yvon Savaria:
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.
IWSOC 2005: 557-562 |
| 2004 |
| 2 |  | Hung Tien Bui,
Yvon Savaria:
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.
ISCAS (4) 2004: 369-372 |
| 1 |  | Hung Tien Bui,
Yvon Savaria:
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.
IWSOC 2004: 115-118 |