Philip Brisk

	2012
56		Daniel Grissom, Philip Brisk: A high-performance online assay interpreter for digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2012: 103-106
55		Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne: Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548
54		Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk: Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264
	2011
53		Quentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, Fabrice Rastello: Graph-coloring and treescan register allocation using repairing. CASES 2011: 45-54
52		Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne: A first step towards automatic application of power analysis countermeasures. DAC 2011: 230-235
51		Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne: Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246
50		Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne: Compressor tree synthesis on commercial high-performance FPGAs. TRETS 4(4): 39 (2011)
	2010
49		Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul: A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712
48		Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24
47		Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne: Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC 2010: 126-140
46		Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne: Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. VLSI Syst. 18(4): 578-590 (2010)
45		Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 341-354 (2010)
44		Philip Brisk, Ajay K. Verma, Paolo Ienne: An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1096-1109 (2010)
	2009
43		Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne: Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209
42		Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219
41		Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36
40		José Luis Ayala, David Atienza, Philip Brisk: Thermal-aware data flow analysis. DAC 2009: 613-614
39		Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne: FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270
38		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286
37		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL 2009: 242-249
36		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510
35		Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne: MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197
34		Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD 2009: 689-696
33		Ajay K. Verma, Philip Brisk, Paolo Ienne: Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD 2009: 797-804
32		Ajay K. Verma, Philip Brisk, Paolo Ienne: Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic 2009: 213-218
31		Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne: Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP 2009: 114-121
30		Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne: Arithmetic optimization for custom instruction set synthesis. SASP 2009: 54-57
29		Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne: Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS 2009: 115-120
28		Ani Nahapetian, Philip Brisk, Soheil Ghiasi, Majid Sarrafzadeh: An approximation algorithm for scheduling on heterogeneous reconfigurable resources. ACM Trans. Embedded Comput. Syst. 9(1): (2009)
27		Philip Brisk, Ajay K. Verma, Paolo Ienne: Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Design Autom. for Emb. Sys. 13(1-2): 115-137 (2009)
26		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2): (2009)
25		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. TRETS 2(3): (2009)
	2008
24		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143
23		Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339
22		Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216
21		Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248
20		Ajay K. Verma, Philip Brisk, Paolo Ienne: Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255
19		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261
18		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180
17		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190
16		Jani Boutellier, Veeranjaneyulu Sadhanala, Christophe Lucarz, Philip Brisk, Marco Mattavelli: Scheduling of dataflow models within the Reconfigurable Video Coding framework. SiPS 2008: 182-187
15		Ajay K. Verma, Philip Brisk, Paolo Ienne: Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1761-1774 (2008)
	2007
14		Ajay K. Verma, Philip Brisk, Paolo Ienne: Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134
13		Philip Brisk, Ajay K. Verma, Paolo Ienne: An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217
12		Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar: Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337
11		Ajay K. Verma, Philip Brisk, Paolo Ienne: Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409
10		Philip Brisk, Ajay K. Verma, Paolo Ienne: Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179
9		Philip Brisk, Majid Sarrafzadeh: Interference graphs for procedures in static single information form are interval graphs. SCOPES 2007: 101-110
	2006
8		Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh: Layout driven data communication optimization for high level synthesis. DATE 2006: 1185-1190
7		Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh: Optimal register sharing for high-level synthesis of SSA form programs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 772-779 (2006)
	2005
6		Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid Sarrafzadeh: A dictionary construction technique for code compression systems with echo instructions. LCTES 2005: 105-114
5		Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh: Adaptive and fault tolerant medical vest for life-critical medical monitoring. SAC 2005: 272-279
	2004
4		Philip Brisk, Adam Kaplan, Majid Sarrafzadeh: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. DAC 2004: 395-400
3		Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh: Instruction Selection for Compilers that Target Architectures with Echo Instructions. SCOPES 2004: 229-243
	2003
2		Adam Kaplan, Philip Brisk, Ryan Kastner: Data communication estimation and reduction for reconfigurable systems. DAC 2003: 616-621
	2002
1		Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh: Instruction generation and regularity extraction for reconfigurable processors. CASES 2002: 262-269

Coauthor Index

1	Panagiotis Athanasopoulos	[17] [26] [34] [36] [38]
2	David Atienza (David Atienza Alonso)	[40]
3	José Luis Ayala (José L. Ayala)	[40]
4	Stéphane Badel	[42]
5	Ali Galip Bayrak	[52]
6	Benoit Boissinot	[53]
7	Jani Boutellier	[16] [29]
8	Forrest Brewer	[8]
9	Samuel Burri	[47]
10	Alessandro Cevrero	[17] [22] [26] [29] [36] [38] [39] [42]
11	Edoardo Charbon	[21] [35] [41] [47]
12	Quentin Colombet	[53]
13	Foad Dabiri	[5] [7]
14	Nithin George	[54]
15	Soheil Ghiasi	[28]
16	Wenrui Gong	[8]
17	Daniel Grissom	[56]
18	Frank K. Gürkaynak	[17] [22] [26]
19	Sebastian Hack	[53]
20	Xin Hao	[8]
21	Paolo Ienne	[10] [11] [12] [13] [14] [15] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [54] [55]
22	Roozbeh Jafari	[5] [7]
23	Adam Kaplan	[1] [2] [4] [8]
24	Ryan Kastner	[1] [2] [8]
25	Theo Kluter	[21] [31] [35] [41] [42] [47]
26	Anshul Kumar	[49]
27	Yusuf Leblebici	[17] [22] [26] [34] [36] [38] [42]
28	Guy Lemieux (Guy G. Lemieux, Guy G. F. Lemieux)	[54]
29	Christophe Lucarz	[16]
30	Jamie Macbeth	[6]
31	Marco Mattavelli	[16]
32	Yehdhih Ould Mohammed Moctar	[54]
33	Ani Nahapetian	[3] [6] [28]
34	Arkosnato Neogy	[50]
35	Seyed Hosein Attarzadeh Niaki	[22] [26]
36	Chrysostomos Nicopoulos	[22] [26]
37	David Novo	[55]
38	Arun Paidimarri	[39]
39	Hadi Parandeh-Afshar	[12] [17] [18] [19] [24] [25] [26] [36] [37] [38] [46] [48] [50] [51] [54]
40	Kolin Paul	[49]
41	Nagaraju Pothineni	[49]
42	Fabrice Rastello	[53]
43	Francesco Regazzoni	[42] [52]
44	Veeranjaneyulu Sadhanala	[16]
45	Lazar Saranovac	[55]
46	Majid Sarrafzadeh	[1] [3] [4] [5] [6] [7] [8] [9] [28]
47	Maurizio Skerlj	[36] [38]
48	François-Xavier Standaert	[42] [52]
49	Mirjana Stojilovic	[55]
50	Nigel P. Topham	[31]
51	Ajay K. Verma	[10] [11] [12] [13] [14] [15] [17] [20] [23] [26] [27] [30] [32] [33] [43] [44] [45] [46] [48]
52	Amit Verma	[43] [48]
53	Grace Zgheib	[51]
54	Yi Zhu	[30]
55	Marcela Zuluaga	[31]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page