C. Brej

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2009

2 Padnamabhan Balasubramanian, D. A. Edwards, C. Brej: Self-timed full adder designs based on hybrid input encoding. DDECS 2009: 56-61

2005

1 C. Brej, Jim D. Garside: A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design 2005: 368-373

	2009
2		Padnamabhan Balasubramanian, D. A. Edwards, C. Brej: Self-timed full adder designs based on hybrid input encoding. DDECS 2009: 56-61
	2005
1		C. Brej, Jim D. Garside: A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design 2005: 368-373

Coauthor Index

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team —

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1	Padnamabhan Balasubramanian	[2]
2	D. A. Edwards	[2]
3	Jim D. Garside	[1]