Daniel Brand

	2010
34		Marcio Buss, Daniel Brand, Vugranam C. Sreedhar, Stephen A. Edwards: A novel analysis space for pointer analysis and its application for bug finding. Sci. Comput. Program. 75(11): 921-942 (2010)
	2008
33		Marcio Buss, Daniel Brand, Vugranam C. Sreedhar, Stephen A. Edwards: Flexible pointer analysis using assign-fetch graphs. SAC 2008: 234-239
	2007
32		Daniel Brand, Marcio Buss, Vugranam C. Sreedhar: Evidence-Based Analysis and Inferring Preconditions for Bug Detection. ICSM 2007: 44-53
	2002
31		John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 46(6): 691-708 (2002)
	2000
30		Daniel Brand: A Software Falsifier. ISSRE 2000: 174-185
29		John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan: LSS: A system for production logic synthesis. IBM Journal of Research and Development 44(1): 157-166 (2000)
	1998
28		Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok: Don't cares in synthesis: theoretical pitfalls and practical solutions. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 285-304 (1998)
	1996
27		Daniel Brand, Chandramouli Visweswariah: Inaccuracies in power estimation during logic synthesis. ICCAD 1996: 388-394
26		Leon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler: BooleDozer: Logic synthesis for ASICs. IBM Journal of Research and Development 40(4): 407-430 (1996)
	1995
25		Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash: Efficient use of large don't cares in high-level and logic synthesis. ICCAD 1995: 272-278
24		Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok: Be careful with don't cares. ICCAD 1995: 83-86
	1994
23		Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain: Incremental synthesis. ICCAD 1994: 14-18
22		Daniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm: In the Driver's Seat of BooleDozer. ICCD 1994: 518-521
21		Daniel Brand, Vijay S. Iyengar: Identification of redundant delay faults. IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 553-565 (1994)
	1993
20		Daniel Brand: Verification of large synthesized designs. ICCAD 1993: 534-537
19		Daniel Brand, Tsutomu Sasao: Minimization of AND-EXOR Expressions Using Rewrite Rules. IEEE Trans. Computers 42(5): 568-576 (1993)
18		Daniel Brand: Exhaustive simulation need not require an exponential number of tests. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1635-1641 (1993)
	1992
17		Daniel Brand: Exhaustive simulation need not require an exponential number of tests. ICCAD 1992: 98-101
16		Daniel Brand, Vijay S. Iyengar: Identification of Single Gate Delay Fault Redundancies. ICCD 1992: 24-28
	1989
15		Daniel Brand, Vijay S. Iyengar: Synthesis of Pseudo-Random Pattern Testable Designs. ITC 1989: 501-508
	1988
14		Daniel Brand, Vijay S. Iyengar: Timing Analysis Using Functional Analysis. IEEE Trans. Computers 37(10): 1309-1315 (1988)
	1986
13		William H. Joyner Jr., Louise Trevillyan, Daniel Brand, Theresa A. Nix, Steven C. Gundersen: Technology adaption in logic synthesis. DAC 1986: 94-100
12		Daniel Brand: Detecting Sneak Paths in Transistor Networks. IEEE Trans. Computers 35(3): 274-278 (1986)
	1985
11		John A. Darringer, Daniel Brand, William H. Joyner Jr., Louise Trevillyan, John V. Gerbi: Production logic synthesis. ACM Conference on Computer Science 1985: 13-16
	1984
10		John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan: LSS: A System for Production Logic Synthesis. IBM Journal of Research and Development 28(5): 537-545 (1984)
	1983
9		Daniel Brand: Redundancy and Don't Cares in Logic Synthesis. IEEE Trans. Computers 32(10): 947-952 (1983)
8		Daniel Brand, Pitro Zafiropulo: On Communicating Finite-State Machines J. ACM 30(2): 323-342 (1983)
	1979
7		William C. Carter, William H. Joyner Jr., Daniel Brand: Symbolic simulation for correct machine design. DAC 1979: 280-286
	1978
6		William H. Joyner Jr., William C. Carter, Daniel Brand: Using Machine Descriptions in Program Verification. Jerusalem Conference on Information Technology 1978: 515-522
5		Daniel Brand, William H. Joyner Jr.: Verification of Protocols Using Symbolic Execution. Computer Networks 2: 351-360 (1978)
4		Daniel Brand: Path Calculus in Program Verification. J. ACM 25(4): 630-651 (1978)
	1976
3		Daniel Brand: Proving Programs Incorrect. ICALP 1976: 201-227
2		Daniel Brand: Analytic Resolution in Theorem Proving. Artif. Intell. 7(4): 285-318 (1976)
	1975
1		Daniel Brand: Proving Theorems with the Modification Method. SIAM J. Comput. 4(4): 412-430 (1975)

Coauthor Index

1	Reinaldo A. Bergamaschi	[24] [25] [28] [31]
2	Michel R. C. M. Berkelaar	[25]
3	Subhrajit Bhattacharya	[31]
4	Marcio Buss	[32] [33] [34]
5	William C. Carter	[6] [7]
6	Han Hsun Chao	[26]
7	Robert F. Damiano	[22]
8	John A. Darringer	[10] [11] [29] [31]
9	Anthony D. Drumm	[22] [23] [26]
10	Stephen A. Edwards	[33] [34]
11	David J. Geiger	[26]
12	John V. Gerbi	[10] [11] [29]
13	Lukas P. P. P. van Ginneken	[22]
14	Steven C. Gundersen	[13]
15	Andreas Herkersdorf	[31]
16	Nathaniel Hieter	[26]
17	Vijay S. Iyengar	[14] [15] [16] [21]
18	William H. Joyner Jr.	[5] [6] [7] [10] [11] [13] [29]
19	Sandip Kundu	[23]
20	David S. Kung	[26]
21	Joseph K. Morrell	[31]
22	Indira Nair	[31]
23	Prakash Narain	[23]
24	Theresa A. Nix	[13]
25	Peter J. Osler	[26]
26	Shiv Prakash	[25]
27	Lakshmi N. Reddy	[26]
28	Patricia Sagmeister	[31]
29	Tsutomu Sasao	[19]
30	Youngsoo Shin	[31]
31	Vugranam C. Sreedhar	[32] [33] [34]
32	Leon Stok	[24] [25] [26] [28]
33	Andrew J. Sullivan	[26]
34	Louise Trevillyan	[10] [11] [13] [29]
35	Chandramouli Visweswariah	[27]
36	Pitro Zafiropulo	[8]

Colors in the list of coauthors

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