Linda E. M. Brackenbury

L. E. M. Brackenbury

	2010
8		Linda E. M. Brackenbury, Luis A. Plana, Jeffrey Pepper: System-on-Chip Design and Implementation. IEEE Trans. Education 53(2): 272-281 (2010)
	2008
7		Wei Shao, Linda E. M. Brackenbury: Pre-processing of convolutional codes for reducing decoding power consumption. ICASSP 2008: 2957-2960
	2007
6		Linda E. M. Brackenbury, Wei Shao: Lowering power in an experimental RISC processor. Microprocessors and Microsystems 31(5): 360-368 (2007)
	2004
5		Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury: An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215
	2001
4		P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber: A Low-Power Self-Timed Viterbi Decoder. ASYNC 2001: 15-24
3		Mike J. G. Lewis, L. E. M. Brackenbury: Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. ASYNC 2001: 4-14
	2000
2		Mike J. G. Lewis, L. E. M. Brackenbury: An Instruction Buffer for a Low-Power DSP. ASYNC 2000: 176-
	1999
1		Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury: Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ASYNC 1999: 27-35

Coauthor Index

1	J. Mike Cumpstey	[4]
2	Aristides Efthymiou	[5]
3	Stephen B. Furber (Steve Furber)	[4]
4	Jim D. Garside	[1] [5]
5	Mike J. G. Lewis	[1] [2] [3]
6	Jeffrey Pepper	[8]
7	Luis A. Plana	[8]
8	P. A. Riocreux	[4]
9	Wei Shao	[6] [7]
10	W. Suntiamorntut	[5]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page