 | 2011 |
|---|
| 5 |       | Garo Bournoutian,
Alex Orailoglu:
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors.
CODES+ISSS 2011: 89-98 |
| 2010 |
|---|
| 4 | | Garo Bournoutian,
Alex Orailoglu:
Dynamic, non-linear cache architecture for power-sensitive mobile processors.
CODES+ISSS 2010: 187-194 |
| 3 | | Garo Bournoutian,
Alex Orailoglu:
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.
Design Autom. for Emb. Sys. 14(3): 309-326 (2010) |
| 2009 |
|---|
| 2 | | Garo Bournoutian,
Alex Orailoglu:
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.
CASES 2009: 117-126 |
| 2008 |
|---|
| 1 | | Garo Bournoutian,
Alex Orailoglu:
Miss reduction in embedded processors through dynamic, power-friendly cache design.
DAC 2008: 304-309 |
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