 | 2011 |
|---|
| 8 |       | Abdelmajid Bouajila,
Johannes Zeppenfeld,
Walter Stechele,
Andreas Herkersdorf:
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors.
DDECS 2011: 225-230 |
| 7 | | Abdelmajid Bouajila,
Johannes Zeppenfeld,
Walter Stechele,
Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel,
Andreas Herkersdorf:
Autonomic System on Chip Platform.
Organic Computing 2011: 413-425 |
| 6 | | Johannes Zeppenfeld,
Abdelmajid Bouajila,
Walter Stechele,
Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel,
Andreas Herkersdorf:
Applying ASoC to Multi-core Applications for Workload Management.
Organic Computing 2011: 461-472 |
| 2010 |
|---|
| 5 | | Matthias May,
Norbert Wehn,
Abdelmajid Bouajila,
Johannes Zeppenfeld,
Walter Stechele,
Andreas Herkersdorf,
Daniel Ziener,
Jürgen Teich:
A rapid prototyping system for error-resilient multi-processor systems-on-chip.
DATE 2010: 375-380 |
| 2008 |
|---|
| 4 | | Johannes Zeppenfeld,
Abdelmajid Bouajila,
Walter Stechele,
Andreas Herkersdorf:
Learning Classifier Tables for Autonomic Systems on Chip.
GI Jahrestagung (2) 2008: 771-778 |
| 2006 |
|---|
| 3 | | Abdelmajid Bouajila,
Andreas Bernauer,
Andreas Herkersdorf,
Wolfgang Rosenstiel,
Oliver Bringmann,
Walter Stechele:
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs.
BICC 2006: 107-113 |
| 2 | | Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel,
Abdelmajid Bouajila,
Walter Stechele,
Andreas Herkersdorf:
An Architecture for Runtime Evaluation of SoC Reliability.
GI Jahrestagung (1) 2006: 177- |
| 1 | | Abdelmajid Bouajila,
Johannes Zeppenfeld,
Walter Stechele,
Andreas Herkersdorf,
Andreas Bernauer,
Oliver Bringmann,
Wolfgang Rosenstiel:
Organic Computing at the System on Chip Level.
VLSI-SoC 2006: 338-341 |
Data released under the ODC-BY 1.0 license — See also our legal information page