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| 2012 | ||
|---|---|---|
| 52 | J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay: Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537 | |
| 51 | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash Memories. J. Electronic Testing 28(2): 215-228 (2012) | |
| 2011 | ||
| 50 | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 | |
| 49 | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine: Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460 | |
| 48 | Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, X. Wen: Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510 | |
| 47 | Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel: Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 | |
| 46 | Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194 | |
| 45 | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358 | |
| 44 | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364 | |
| 43 | Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch: On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT 2011: 226-232 | |
| 42 | Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301 | |
| 41 | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda: A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. European Test Symposium 2011: 153-158 | |
| 40 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8 | |
| 2010 | ||
| 39 | Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo: A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105 | |
| 38 | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer: A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242 | |
| 37 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856 | |
| 36 | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen: Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 | |
| 35 | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda: An Exact and Efficient Critical Path Tracing Algorithm. DELTA 2010: 164-169 | |
| 34 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269 | |
| 33 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. European Test Symposium 2010: 132-137 | |
| 32 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Setting test conditions for improving SRAM reliability. European Test Symposium 2010: 257 | |
| 31 | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. European Test Symposium 2010: 81-86 | |
| 30 | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed: Is test power reduction through X-filling good enough? ITC 2010: 805 | |
| 29 | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 | |
| 28 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80 | |
| 27 | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59(3): 289-300 (2010) | |
| 26 | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed: A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electronics 6(2): 359-374 (2010) | |
| 2009 | ||
| 25 | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer: Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360 | |
| 24 | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute: Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269 | |
| 23 | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda: An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS 2009: 50-55 | |
| 22 | Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute: A case study on logic diagnosis for System-on-Chip. ISQED 2009: 253-259 | |
| 21 | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard: NAND flash testing: A preliminary study on actual defects. ITC 2009: 1 | |
| 20 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Paolo Prinetto: Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. IEEE Design & Test of Computers 26(3): 16-24 (2009) | |
| 19 | Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Is triple modular redundancy suitable for yield improvement? IET Computers & Digital Techniques 3(6): 581-592 (2009) | |
| 2008 | ||
| 18 | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi: SoC Symbolic Simulation: a case study on delay fault testing. DDECS 2008: 320-325 | |
| 17 | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215 | |
| 16 | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Using TMR Architectures for Yield Improvement. DFT 2008: 7-15 | |
| 15 | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166 | |
| 14 | Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand: A Modular Memory BIST for Optimized Memory Repair. IOLTS 2008: 171-172 | |
| 13 | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1 | |
| 12 | Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10 | |
| 11 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: March Test Generation Revealed. IEEE Trans. Computers 57(12): 1704-1713 (2008) | |
| 2007 | ||
| 10 | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242 | |
| 9 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani: A Functional Verification Based Fault Injection Environment. DFT 2007: 114-122 | |
| 8 | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: DERRIC: A Tool for Unified Logic Diagnosis. European Test Symposium 2007: 13-20 | |
| 7 | Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs. IET Computers & Digital Techniques 1(3): 237-245 (2007) | |
| 2006 | ||
| 6 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Automatic march tests generations for static linked faults in SRAMs. DATE 2006: 1258-1263 | |
| 5 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. DDECS 2006: 157-158 | |
| 4 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Automatic March Tests Generation for Multi-Port SRAMs. DELTA 2006: 385-392 | |
| 3 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: A 22n March Test for Realistic Static Linked Faults in SRAMs. European Test Symposium 2006: 49-54 | |
| 2 | Alberto Bosio, Giovanni Righini: A dynamic programming algorithm for the single-machine scheduling problem with deteriorating processing times. Electronic Notes in Discrete Mathematics 25: 139-142 (2006) | |
| 2005 | ||
| 1 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: March AB, March AB1: new March tests for unlinked dynamic memory faults. ITC 2005: 8 | |
Colors in the list of coauthors
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