 | 2009 |
| 8 |  | Di Wang,
Vyas Venkataraman,
Zhen Wang,
Wei Qin,
Hangsheng Wang,
Mrinal Bose,
Jayanta Bhadra:
Accelerating multi-party scheduling for transaction-level modeling.
ACM Great Lakes Symposium on VLSI 2009: 339-344 |
| 7 |  | Mrinal Bose,
Prashant Naphade,
Jayanta Bhadra,
Hillel Miller:
An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs.
ISQED 2009: 377-381 |
| 6 |  | Vyas Venkataraman,
Di Wang,
Atabak Mahram,
Wei Qin,
Mrinal Bose,
Jayanta Bhadra:
Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models.
ISVLSI 2009: 241-246 |
| 5 |  | Francisco Torres,
Rohit Srivastava,
Javier Ruiz,
Charles H.-P. Wen,
Mrinal Bose,
Jayanta Bhadra:
Portable simulation/emulation stimulus on an industrial-strength SoC.
ITC 2009: 1 |
| 4 |  | Vyas Venkataraman,
Di Wang,
Wei Qin,
Mrinal Bose,
Jayanta Bhadra:
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling.
MTV 2009: 3-8 |
| 2003 |
| 3 |  | Mrinal Bose,
Mark H. Nodine,
William R. Jurasz Jr.,
Vlad Zavadsky,
Arvind Chodavadia,
Lincoln R. Nunes:
Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification.
MTV 2003: 7-10 |
| 2001 |
| 2 |  | Mrinal Bose,
Elizabeth M. Rudnick,
Magdy S. Abadir:
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.
IOLTW 2001: 65- |
| 1999 |
| 1 |  | Partha Pratim Chakrabarti,
Pallab Dasgupta,
Partha Pratim Das,
Arnob Roy,
Shuvendu K. Lahiri,
Mrinal Bose:
Controlling State Explosion in Static Simulation by Selective Composition.
VLSI Design 1999: 226-231 |