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| 2010 | ||
|---|---|---|
| 53 | Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic: Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1436-1448 (2010) | |
| 2009 | ||
| 52 | Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic: MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80 | |
| 51 | Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre: High-level symbolic simulation for automatic model extraction. DDECS 2009: 218-221 | |
| 50 | Yann Oddos, Katell Morin-Allory, Dominique Borrione: From Assertion-Based Verification to Assertion-Based Synthesis. VLSI-SoC 2009: 94-117 | |
| 49 | Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: A Formal Approach to the Verification of Networks on Chip. EURASIP J. Emb. Sys. 2009: (2009) | |
| 2008 | ||
| 48 | Yann Oddos, Katell Morin-Allory, Dominique Borrione: Assertion-Based Design with Horus. MEMOCODE 2008: 75-76 | |
| 47 | Dominique Borrione, Amr Helmy, Laurence Pierre, Julien Schmaltz: Executable formal specification and validation of NoC communication infrastructures. SBCCI 2008: 176-181 | |
| 46 | Julien Schmaltz, Dominique Borrione: A functional formalization of on chip communications. Formal Asp. Comput. 20(3): 241-258 (2008) | |
| 2007 | ||
| 45 | Yann Oddos, Katell Morin-Allory, Dominique Borrione: Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS 2007: 383-388 | |
| 44 | Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione: Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290 | |
| 43 | Dominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz: A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study. NOCS 2007: 127-136 | |
| 42 | Katell Morin-Allory, Eric Gascard, Dominique Borrione: Synthesis of Property Monitors for Online Fault Detection. Journal of Circuits, Systems, and Computers 16(6): 943-960 (2007) | |
| 2006 | ||
| 41 | Julien Schmaltz, Dominique Borrione: Towards a formal theory of on chip communications in the ACL2 logic. ACL2 2006: 47-56 | |
| 40 | Katell Morin-Allory, Dominique Borrione: Proven correct monitors from PSL specifications. DATE 2006: 1246-1251 | |
| 39 | Katell Morin-Allory, Dominique Borrione: On-line Monitoring of Properties Built on Regular Expressions. FDL 2006: 249-255 | |
| 38 | Katell Morin-Allory, Laurent Fesquet, Dominique Borrione: Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102 | |
| 37 | Julien Schmaltz, Dominique Borrione: Formalizing On Chip Communications in a Functional Style. Trustworthy Software 2006 | |
| 36 | Yann Oddos, Katell Morin-Allory, Dominique Borrione: On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC 2006: 397-402 | |
| 2005 | ||
| 35 | Dominique Borrione, Wolfgang J. Paul: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings Springer 2005 | |
| 34 | Ghiath Al Sammane, Dominique Borrione, Remy Chevallier: Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. ACM Great Lakes Symposium on VLSI 2005: 260-263 | |
| 33 | Julien Schmaltz, Dominique Borrione: A Generic Network on Chip Model. TPHOLs 2005: 310-325 | |
| 32 | Diana Toma, Dominique Borrione: Formal Verification of a SHA-1 Circuit Core Using ACL2. TPHOLs 2005: 326-341 | |
| 2004 | ||
| 31 | Diana Toma, Dominique Borrione, Ghiath Al Sammane: Combining Several Paradigms for Circuit Validation and Verification. CASSIS 2004: 229-249 | |
| 30 | Julien Schmaltz, Dominique Borrione: A Functional Approach to the Formal Specification of Networks on Chip. FMCAD 2004: 52-66 | |
| 29 | Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione: TheoSim: combining symbolic simulation and theorem proving for hardware verification. SBCCI 2004: 60-65 | |
| 2003 | ||
| 28 | Ghiath Al Sammane, Diana Toma, Julien Schmaltz, Pierre Ostier, Dominique Borrione: Constrained Symbolic Simulation with Mathematica and ACL2. CHARME 2003: 150-157 | |
| 27 | Dominique Borrione, Menouer Boubekeur: Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications. FDL 2003: 481-492 | |
| 26 | Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni: An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279 | |
| 25 | Emil Dumitrescu, Dominique Borrione: Symbolic Simulation as a Simplifying Strategy for SoC Verification. IWSOC 2003: 378-383 | |
| 24 | Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni: Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91 | |
| 2002 | ||
| 23 | Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud: Formal Verification Techniques: Industrial Status and Perspectives. DATE 2002: 1050 | |
| 22 | Jorgiano Vidal, David Déharbe, Dominique Borrione: Improving Static Ordering of BDDs for Reachability Analysis. IWLS 2002: 73-77 | |
| 2001 | ||
| 21 | S. Reda, Ayman M. Wahba, Ashraf M. Salem, Dominique Borrione, M. Ghonaimy: On the use of don't cares during symbolic reachability analysis. ISCAS (5) 2001: 121-124 | |
| 2000 | ||
| 20 | Dominique Borrione, Julia Dushina, Laurence V. Pierre: A compositional model for the functional verification of high-level synthesis results. IEEE Trans. VLSI Syst. 8(5): 526-530 (2000) | |
| 19 | Vanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin: Using the ACL2 Theorem Prover to Reason about VHDL Components. RITA 7(1): 129-148 (2000) | |
| 1999 | ||
| 18 | Raimund Ubar, Dominique Borrione: Design Error Diagnosis in Digital Circuits without Error Model. VLSI 1999: 281-292 | |
| 1997 | ||
| 17 | Dominique Borrione, F. Vestman, H. Bouamama: An approach to Verilog-VHDL interoperability for synchronous designs. CHARME 1997: 65-87 | |
| 16 | Ayman M. Wahba, Dominique Borrione: Connection error location and correction in combinational circuits. ED&TC 1997: 235-241 | |
| 1996 | ||
| 15 | Dominique Borrione, H. Bouamama, David Déharbe, C. Le Faou, Ayman M. Wahba: HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. FMCAD 1996: 450-467 | |
| 14 | Ayman M. Wahba, Dominique Borrione: A method for automatic design error location and correction in combinational logic circuits. J. Electronic Testing 8(2): 113-127 (1996) | |
| 1995 | ||
| 13 | Ayman M. Wahba, Dominique Borrione: Design error diagnosis in sequential circuits. CHARME 1995: 171-188 | |
| 12 | David Déharbe, Dominique Borrione: Semantics of a verification-oriented subset of VHDL. CHARME 1995: 293-310 | |
| 11 | Dominique Borrione, Ashraf M. Salem: Denotational Semantics of a Synchronous VHDL Subset. Formal Methods in System Design 7(1/2): 53-71 (1995) | |
| 1994 | ||
| 10 | Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto: A process algebra interpretation of a verification oriented overlanguage of VHDL. EURO-DAC 1994: 506-511 | |
| 1992 | ||
| 9 | Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem: Formal Verification of VHDL Descriptions in the Prevail Environment. IEEE Design & Test of Computers 9(2): 42-56 (1992) | |
| 8 | Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby: Three Decades of HDLs: Part II, Conlan Through Verilog. IEEE Design & Test of Computers 9(3): 54-63 (1992) | |
| 1989 | ||
| 7 | Dominique Borrione, Paolo Prinetto: Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis. IFIP Congress 1989: 233-240 | |
| 1983 | ||
| 6 | Robert Piloty, Dominique Borrione, Mario Barbacci, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN Report Springer 1983 | |
| 1982 | ||
| 5 | Robert Piloty, Dominique Borrione: The conlan project: Status and future plans. DAC 1982: 202-212 | |
| 1980 | ||
| 4 | Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: basic principles. AFIPS National Computer Conference 1980: 209-217 | |
| 3 | Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: language derivation. AFIPS National Computer Conference 1980: 219-227 | |
| 2 | Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: CONLAN: a formal construction method for hardware description languages: language application. AFIPS National Computer Conference 1980: 229-236 | |
| 1 | Robert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly: An Overview of CONLAN: A Formal Construction Method for Hardware Description Language. IFIP Congress 1980: 199-204 | |
Colors in the list of coauthors
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