 | 2011 |
|---|
| 10 |       | Grzegorz Borowik,
Andrzej Krasniewski:
Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs.
EUROCAST (2) 2011: 327-334 |
| 9 | | Grzegorz Borowik,
Andrzej Paszkiewicz:
Method of Generating Irreducible Polynomials over GF(3) on the Basis of Trinomials.
EUROCAST (2) 2011: 335-342 |
| 8 | | Grzegorz Borowik,
Tadeusz Luba,
Pawel Tomaszewicz:
On Memory Capacity to Implement Logic Functions.
EUROCAST (2) 2011: 343-350 |
| 7 | | Grzegorz Borowik,
Tadeusz Luba,
Dawid Zydek:
Reduction of Knowledge Representation Using Logic Minimization Techniques.
ICSEng 2011: 482-485 |
| 6 | | Grzegorz Borowik,
Andrzej Paszkiewicz:
Hardware Accelerator for Generating Primitive Polynomials over GF(3).
ICSEng 2011: 486-487 |
| 5 | | Grzegorz Borowik,
Andrzej Krasniewski:
A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs.
ICSEng 2011: 488-489 |
| 4 | | Dawid Zydek,
Henry Selvaraj,
Grzegorz Borowik,
Tadeusz Luba:
Energy characteristic of a processor allocator and a network-on-chip.
Applied Mathematics and Computer Science 21(2): 385-399 (2011) |
| 2009 |
|---|
| 3 | | Grzegorz Borowik,
Tadeusz Luba,
Bogdan J. Falkowski:
Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories.
DDECS 2009: 230-233 |
| 2 | | Grzegorz Borowik,
Tadeusz Luba:
Decomposing Pattern Matching Circuit.
EUROCAST 2009: 563-570 |
| 2007 |
|---|
| 1 |  | Grzegorz Borowik,
Bogdan J. Falkowski,
Tadeusz Luba:
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs.
DDECS 2007: 99-104 |
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