 | 2011 |
| 11 |  | Youfeng Wu,
Shiliang Hu,
Edson Borin,
Cheng Wang:
A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing.
CGO 2011: 236-245 |
| 10 |  | Edson Borin,
Youfeng Wu,
Mauricio Breternitz Jr.,
Cheng Wang:
LAR-CC: Large atomic regions with conditional commits.
CGO 2011: 54-63 |
| 2010 |
| 9 |  | Edson Borin,
Youfeng Wu,
Cheng Wang,
Wei Liu,
Mauricio Breternitz Jr.,
Shiliang Hu,
Esfir Natanzon,
Shai Rotem,
Roni Rosner:
TAO: two-level atomicity for dynamic binary optimizations.
CGO 2010: 12-21 |
| 8 |  | João Porto,
Guido Araujo,
Edson Borin,
Youfeng Wu:
Trace Execution Automata in Dynamic Binary Translation.
ISCA Workshops 2010: 99-116 |
| 2009 |
| 7 |  | Cheng Wang,
Youfeng Wu,
Edson Borin,
Shiliang Hu,
Wei Liu,
Dave Sager,
Tin-fook Ngai,
Jesse Fang:
Dynamic parallelization of single-threaded binary programs using speculative slicing.
ICS 2009: 158-168 |
| 6 |  | Edson Borin,
Youfeng Wu:
Characterization of DBT overhead.
IISWC 2009: 178-187 |
| 2006 |
| 5 |  | Edson Borin,
Cheng Wang,
Youfeng Wu,
Guido Araujo:
Software-Based Transparent and Comprehensive Control-Flow Error Detection.
CGO 2006: 333-345 |
| 4 |  | Edson Borin,
Mauricio Breternitz Jr.,
Youfeng Wu,
Guido Araujo:
Clustering-Based Microcode Compression.
ICCD 2006 |
| 2005 |
| 3 |  | Nahri Moreano,
Edson Borin,
Cid C. de Souza,
Guido Araujo:
Efficient datapath merging for partially reconfigurable architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 969-980 (2005) |
| 2 |  | Edson Borin,
Cheng Wang,
Youfeng Wu,
Guido Araujo:
Dynamic binary control-flow errors detection.
SIGARCH Computer Architecture News 33(5): 15-20 (2005) |
| 2004 |
| 1 |  | Edson Borin,
Felipe Klein,
Nahri Moreano,
Rodolfo Azevedo,
Guido Araujo:
Fast instruction set custornization.
ESTImedia 2004: 53-58 |