 | 2012 |
|---|
| 8 |       | Xuan You Tan,
David Boland,
George A. Constantinides:
FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores.
ARC 2012: 290-301 |
| 7 | | David Boland,
George A. Constantinides:
A scalable approach for automated precision analysis.
FPGA 2012: 185-194 |
| 2011 |
|---|
| 6 | | Christophe Le Lann,
David Boland,
George A. Constantinides:
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA.
ARC 2011: 287-295 |
| 5 | | David Boland,
George A. Constantinides:
Bounding Variable Values and Round-Off Effects Using Handelman Representations.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1691-1704 (2011) |
| 4 | | David Boland,
George A. Constantinides:
Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods.
TRETS 4(3): 22 (2011) |
| 2010 |
|---|
| 3 | | David Boland,
George A. Constantinides:
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods.
ARC 2010: 169-181 |
| 2 | | David Boland,
George A. Constantinides:
Automated Precision Analysis: A Polynomial Algebraic Approach.
FCCM 2010: 157-164 |
| 2008 |
|---|
| 1 | | David Boland,
George A. Constantinides:
An FPGA-based implementation of the MINRES algorithm.
FPL 2008: 379-384 |
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