 | 2011 |
|---|
| 6 |       | Anton Blad,
Oscar Gustafsson:
FPGA implementation of rate-compatible QC-LDPC code decoder.
ECCTD 2011: 777-780 |
| 2010 |
|---|
| 5 | | Anton Blad,
Oscar Gustafsson:
Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees.
ISCAS 2010: 181-184 |
| 4 | | Meng Zheng,
Zesong Fei,
Xiang Chen,
Jingming Kuang,
Anton Blad:
Power Efficient Partial Repeated Cooperation Scheme with Regular LDPC Code.
VTC Spring 2010: 1-5 |
| 2008 |
|---|
| 3 | | Anton Blad,
Oscar Gustafsson:
Bit-level optimized FIR filter architectures for high-speed decimation applications.
ISCAS 2008: 1914-1917 |
| 2 | | Anton Blad,
Håkan Johansson,
Per Löwenborg:
Multirate Formulation for Mismatch Sensitivity Analysis of Analog-to-Digital Converters That Utilize Parallel ΣΔ-Modulators.
EURASIP J. Adv. Sig. Proc. 2008: (2008) |
| 2006 |
|---|
| 1 | | Anton Blad,
Håkan Johansson,
Per Löwenborg:
A General Formulation of Analog-to-Digital Converters Using Parallel Sigma-Delta Modulators and Modulation Sequences.
APCCAS 2006: 438-441 |
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