 | 2011 |
|---|
| 12 |       | Zdenek Vasícek,
Michal Bidlo:
Evolutionary design of robust noise-specific image filters.
IEEE Congress on Evolutionary Computation 2011: 269-276 |
| 2010 |
|---|
| 11 | | Zdenek Vasícek,
Lukás Sekanina,
Michal Bidlo:
A method for design of impulse bursts noise filters optimized for FPGA implementations.
DATE 2010: 1731-1736 |
| 10 | | Michal Bidlo,
Zdenek Vasícek,
Karel Slaný:
Sorting Network Development Using Cellular Automata.
ICES 2010: 85-96 |
| 2009 |
|---|
| 9 | | Michal Bidlo,
Zdenek Vasícek:
Development of combinational circuits using non-uniform cellular automata: initial results.
GECCO 2009: 1839-1840 |
| 8 | | Michal Bidlo,
Zdenek Vasícek:
Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model.
IEEE Congress on Evolutionary Computation 2009: 2241-2248 |
| 2008 |
|---|
| 7 | | Michal Bidlo,
Zdenek Vasícek:
Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study.
ICES 2008: 106-117 |
| 6 | | Michal Bidlo,
Jaroslav Skarvada:
Instruction-based development: From evolution to generic structures of digital circuits.
KES Journal 12(3): 221-236 (2008) |
| 2007 |
|---|
| 5 | | Michal Bidlo:
Evolutionary Development of Generic Multipliers: Initial Results.
AHS 2007: 405-412 |
| 4 | | Michal Bidlo:
Evolutionary Design of Generic Combinational Multipliers Using Development.
ICES 2007: 77-88 |
| 2005 |
|---|
| 3 | | Michal Bidlo,
Lukás Sekanina:
Providing information from the environment for growing electronic circuits through polymorphic gates.
GECCO Workshops 2005: 242-248 |
| 2 | | Michal Bidlo:
A benchmark for the sorting network problem.
GECCO Workshops 2005: 289-291 |
| 1 | | Lukás Sekanina,
Michal Bidlo:
Evolutionary Design of Arbitrarily Large Sorting Networks Using Development.
Genetic Programming and Evolvable Machines 6(3): 319-347 (2005) |
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