Swarup Bhunia

	2012
119		Kamran Rahmani, Prabhat Mishra, Swarup Bhunia: Memory-based computing for performance and energy improvement in multicore architectures. ACM Great Lakes Symposium on VLSI 2012: 287-290
118		Susmita Sur-Kolay, Swarup Bhunia: Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. VLSI Design 2012: 18-19
117		Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia: SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation. VLSI Design 2012: 304-309
116		Lei Wang, Somnath Paul, Swarup Bhunia: Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. VLSI Design 2012: 340-345
115		Anandaroop Ghosh, Somnath Paul, Swarup Bhunia: Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. VLSI Design 2012: 424-429
	2011
114		Aswin Raghav Krishna, Seetharam Narasimhan, Xinmu Wang, Swarup Bhunia: MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array. CHES 2011: 407-420
113		Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Francis G. Wolff, Srihari Rajgopal, Te-Hao Lee, Mehran Mehregany, Swarup Bhunia: High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches. DATE 2011: 1065-1070
112		Subidh Ali, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Swarup Bhunia: Multi-level attacks: An emerging security concern for cryptographic hardware. DATE 2011: 1176-1179
111		Somnath Paul, Swarup Bhunia: Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). FPGA 2011: 283
110		Seetharam Narasimhan, Xinmu Wang, Dongdong Du, Rajat Subhra Chakraborty, Swarup Bhunia: TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection. HOST 2011: 71-74
109		Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Tatini Mal-Sarkar, Swarup Bhunia: Sequential hardware Trojan: Side-channel aware design and placement. ICCD 2011: 297-300
108		Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia: Embedded Software Security through Key-Based Control Flow Obfuscation. InfoSecHiComNet 2011: 30-44
107		Keerthi Kunaparaju, Seetharam Narasimhan, Swarup Bhunia: VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width. VLSI Design 2011: 310-315
106		Seetharam Narasimhan, Hillel J. Chiel, Swarup Bhunia: Ultra-Low-Power and Robust Digital-Signal-Processing Hardware for Implantable Neural Interface Microsystems. IEEE Trans. Biomed. Circuits and Systems 5(2): 169-178 (2011)
105		Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia: Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Trans. Computers 60(1): 20-34 (2011)
104		Somnath Paul, Swarup Bhunia: Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement. IEEE Trans. VLSI Syst. 19(8): 1368-1379 (2011)
103		Rajat Subhra Chakraborty, Swarup Bhunia: Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation. J. Electronic Testing 27(6): 767-785 (2011)
	2010
102		Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty, Swarup Bhunia: Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection. CHES 2010: 173-187
101		Seetharam Narasimhan, David R. McIntyre, Francis G. Wolff, Yu Zhou, Daniel J. Weyer, Swarup Bhunia: A supply-demand model based scalable energy management system for improved energy utilization efficiency. Green Computing Conference 2010: 97-105
100		Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia: Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST 2010: 13-18
99		David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia: Trustworthy computing in a multi-core system using distributed scheduling. IOLTS 2010: 211-213
98		Somnath Paul, Swarup Bhunia: VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. ISLPED 2010: 37-42
97		Rajat Subhra Chakraborty, Swarup Bhunia: RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. VLSI Design 2010: 405-410
96		Swarup Bhunia, Anand Raghunathan: Special session 11B: Hot topic hardware security: Design, test and verification issues. VTS 2010: 349
95		Somnath Paul, Hamid Mahmoodi, Swarup Bhunia: Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. ACM Trans. Design Autom. Electr. Syst. 15(2): (2010)
94		Tatini Mal-Sarkar, Swarup Bhunia: Collaborative Trust: A Novel Paradigm of Trusted Mobile Computing CoRR abs/1010.2447: (2010)
93		Swarup Bhunia, Rahul Rao: Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair. IEEE Design & Test of Computers 27(6): 4-5 (2010)
92		Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths. IEEE Trans. VLSI Syst. 18(1): 53-65 (2010)
91		Swarup Bhunia: A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010. J. Low Power Electronics 6(3): 375 (2010)
	2009
90		Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia: MERO: A Statistical Approach for Hardware Trojan Detection. CHES 2009: 396-410
89		Rajat Subhra Chakraborty, Seetharam Narasimhan, Swarup Bhunia: Hardware Trojan: Threats and emerging solutions. HLDVT 2009: 166-171
88		David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia: Dynamic Evaluation of Hardware Trust. HOST 2009: 108-111
87		Rajat Subhra Chakraborty, Swarup Bhunia: Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP. HOST 2009: 96-99
86		Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia: A circuit-software co-design approach for improving EDP in reconfigurable frameworks. ICCAD 2009: 109-112
85		Rajat Subhra Chakraborty, Swarup Bhunia: Security against hardware Trojan through a novel application of design obfuscation. ICCAD 2009: 113-116
84		Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia: A variation-aware preferential design approach for memory based reconfigurable computing. ICCAD 2009: 180-183
83		Rajat Subhra Chakraborty, Swarup Bhunia: HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection. IEEE Trans. on CAD of Integrated Circuits and Systems 28(10): 1493-1502 (2009)
82		Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia: Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping. IET Computers & Digital Techniques 3(6): 609-624 (2009)
81		Rajat Subhra Chakraborty, Swarup Bhunia: A study of asynchronous design methodology for robust CMOS-nano hybrid system design. JETC 5(3): (2009)
	2008
80		Matthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia: On-die CMOS voltage droop detection and dynamiccompensation. ACM Great Lakes Symposium on VLSI 2008: 35-40
79		Somnath Paul, Swarup Bhunia: MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. ASP-DAC 2008: 77-82
78		Seetharam Narasimhan, Somnath Paul, Swarup Bhunia: Collective computing based on swarm intelligence. DAC 2008: 349-350
77		Somnath Paul, Swarup Bhunia: Reconfigurable computing using content addressable memory for improved performance and resource usage. DAC 2008: 786-791
76		Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty: Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. DATE 2008: 1362-1365
75		Lawrence Leinweber, Swarup Bhunia: Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. DATE 2008: 373-378
74		Yu Zhou, Somnath Paul, Swarup Bhunia: Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. DATE 2008: 98-103
73		Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia: On-Demand Transparency for Improving Hardware Trojan Detectability. HOST 2008: 48-50
72		Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia: Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. ICCAD 2008: 589-592
71		Rajat Subhra Chakraborty, Swarup Bhunia: Hardware protection and authentication through netlist level obfuscation. ICCAD 2008: 674-677
70		Swarup Bhunia, Kaushik Roy: Low power design under parameter variations. ISLPED 2008: 137-138
69		Rajat Subhra Chakraborty, Swarup Bhunia: Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. ISQED 2008: 697-701
68		Yu Zhou, Somnath Paul, Swarup Bhunia: Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. ISQED 2008: 861-866
67		Swarup Bhunia, Kaushik Roy: Low power design under parameter variations. SoCC 2008: 389-390
66		Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia: Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. VLSI Design 2008: 441-446
65		Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy: Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. IEEE Trans. Computers 57(7): 940-951 (2008)
64		Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Profit Aware Circuit Design Under Process Variations Considering Speed Binning. IEEE Trans. VLSI Syst. 16(7): 806-815 (2008)
63		Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy: Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electronic Testing 24(6): 577-590 (2008)
	2007
62		Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab: Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ASP-DAC 2007: 86-91
61		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE 2007: 1532-1537
60		Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia: Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404
59		Somnath Paul, Swarup Bhunia: Memory based computation using embedded cache for processor yield and reliability improvement. ICCD 2007: 341-346
58		Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy: Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS 2007: 244-252
57		Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia: Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. IOLTS 2007: 29-36
56		Yu Zhou, Shijo Thekkel, Swarup Bhunia: Low power FPGA design using hybrid CMOS-NEMS approach. ISLPED 2007: 14-19
55		Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia: Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. ISQED 2007: 755-760
54		Swarup Bhunia, Kaushik Roy: Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. ITC 2007: 1-10
53		Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Process Variations and Process-Tolerant Design. VLSI Design 2007: 699-704
52		Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia: VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. VTS 2007: 455-460
51		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
50		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies CoRR abs/0710.4663: (2007)
49		Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits CoRR abs/0710.4729: (2007)
48		Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. IEEE Trans. VLSI Syst. 15(6): 660-671 (2007)
47		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1947-1956 (2007)
	2006
46		Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670
45		Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC 2006: 712-717
44		Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE 2006: 856-861
43		Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia: Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867
42		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD 2006: 619-624
41		Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS 2006: 31-36
40		Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006)
39		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2427-2436 (2006)
38		Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2934-2943 (2006)
37		Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1486-1495 (2006)
	2005
36		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175
35		Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409
34		Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484
33		Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141
32		Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. DATE 2005: 224-229
31		Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE 2005: 926-931
30		Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214
29		Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS 2005: 275-280
28		Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ISLPED 2005: 14-19
27		Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ISQED 2005: 358-363
26		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy: Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458
25		Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297
24		Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embedded Comput. Syst. 4(1): 168-188 (2005)
23		Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy: GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Trans. Computers 54(6): 752-766 (2005)
22		Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. VLSI Syst. 13(11): 1213-1224 (2005)
21		Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. VLSI Syst. 13(11): 1286-1295 (2005)
20		Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
19		Swarup Bhunia, Kaushik Roy: A novel wavelet transform-based transient current analysis for fault detection and localization. IEEE Trans. VLSI Syst. 13(4): 503-507 (2005)
18		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J. Electronic Testing 21(2): 147-159 (2005)
17		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. J. Electronic Testing 21(3): 243-255 (2005)
	2004
16		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. DATE 2004: 704-705
15		Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315
14		Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
13		Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy: A Technique to Reduce Power and Test Application Time in BIST. IOLTS 2004: 182-183
12		Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ISQED 2004: 389-394
11		Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar: DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. VLSI Syst. 12(3): 245-254 (2004)
	2003
10		Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy: Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. DATE 2003: 10096-10103
9		Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy: Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT 2003: 191-198
8		Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. HPCA 2003: 113-122
	2002
7		Swarup Bhunia, Hai Li, Kaushik Roy: A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. Asian Test Symposium 2002: 157-
6		Swarup Bhunia, Kaushik Roy, Jaume Segura: A novel wavelet transform based transient current analysis for fault detection and localization. DAC 2002: 361-366
5		Swarup Bhunia, Kaushik Roy: Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. DATE 2002: 1118
4		Arijit Bishnu, Swarup Bhunia, C. A. Murthy, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya: Content based image retrieval: related issues using Euler vector. ICIP (2) 2002: 585-588
3		Swarup Bhunia, Kaushik Roy: Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. VTS 2002: 302-310
	2000
2		Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya: Topological Routing Amidst Polygonal Obstacles. VLSI Design 2000: 274-279
	1999
1		Swarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee: Design, Simulation and Synthesis of an ASIC for Fractal Image Compression. VLSI Design 1999: 544-547

Coauthor Index

1	Tinku Acharya	[4]
2	Amit Agarwal	[28] [48] [65]
3	Subidh Ali	[112]
4	Nilanjan Banerjee	[23] [27] [30] [31] [34] [40] [43] [50]
5	Bhargab B. Bhattacharya	[2] [4]
6	Arijit Bishnu	[4]
7	Fang Cai	[105]
8	Rajat Subhra Chakraborty	[52] [57] [66] [69] [71] [73] [76] [81] [82] [83] [85] [87] [89] [90] [97] [100] [102] [103] [108] [110] [112]
9	Subho Chatterjee	[86]
10	Qikai Chen	[21] [25] [34]
11	Yiran Chen	[8] [11]
12	Hillel J. Chiel	[106]
13	Lih-Yih Chiou	[10] [24]
14	Jung Hwan Choi	[45] [64]
15	Partha Pratim Das	[1]
16	Animesh Datta	[23] [27] [29] [31] [36] [39] [45] [50] [64]
17	Dongdong Du	[100] [102] [110]
18	James D. Gallagher	[28] [48]
19	Anandaroop Ghosh	[115]
20	Debjyoti Ghosh	[9] [13] [14] [20] [26]
21	Soumya K. Ghosh	[1]
22	Swaroop Ghosh	[35] [38] [41] [42] [47] [51] [58] [61] [92]
23	Ashish Goel	[46]
24	Matthew Seetharam A. Holtz	[80]
25	Kunhyuk Kang	[28] [48]
26	Aswin Raghav Krishna	[109] [113] [114] [117]
27	Sivasubramaniam Krishnamurthy	[55] [60]
28	Pramod Kumar	[1]
29	Keerthi Kunaparaju	[107]
30	Malay Kumar Kundu (Malay K. Kundu)	[4]
31	Te-Hao Lee	[113]
32	Lawrence Leinweber	[75]
33	Hai Li	[7] [8] [11]
34	Hamid Mahmoodi (Hamid Mahmoodi-Meimand)	[14] [15] [20] [21] [25] [26] [30] [33] [34] [40] [43] [46] [60] [63] [95]
35	Subhashis Majumder	[2]
36	Tatini Mal-Sarkar	[94] [109]
37	David R. McIntyre	[88] [99] [101]
38	Mehran Mehregany	[113]
39	Prabhat Mishra	[119]
40	Jayanta Mukherjee	[1]
41	Debdeep Mukhopadhyay	[112]
42	Saibal Mukhopadhyay	[14] [20] [29] [31] [32] [36] [37] [39] [45] [49] [50] [53] [64] [72] [84] [86]
43	C. A. Murthy	[4]
44	Seetharam Narasimhan	[78] [80] [89] [100] [101] [102] [106] [107] [108] [109] [110] [113] [114] [117]
45	Patrick Ndai	[58] [65] [92]
46	Christos A. Papachristou	[76] [88] [90] [99] [100]
47	Bipul Chandra Paul (Bipul C. Paul)	[22] [44]
48	Somnath Paul	[52] [55] [57] [59] [60] [66] [68] [72] [73] [74] [77] [78] [79] [82] [84] [86] [90] [95] [98] [100] [104] [105] [111] [115] [116]
49	Nauman Rafique	[92]
50	Anand Raghunathan	[96]
51	Kamran Rahmani	[119]
52	Srihari Rajgopal	[113]
53	Rahul Rao	[93]
54	Arijit Raychowdhury	[12] [15] [16] [17] [18] [22] [30] [33] [38] [40] [41] [44] [63]
55	Kaushik Roy	[3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [53] [54] [58] [61] [63] [64] [65] [67] [70] [92] [100]
56	Daniel G. Saab	[62]
57	Jaume Segura	[6]
58	Ayan Sircar	[2]
59	Susmita Sur-Kolay	[2] [118]
60	Massood Tabib-Azar	[62]
61	Shijo Thekkel	[56]
62	Mithuna Thottethodi	[92]
63	T. N. Vijaykumar	[8] [11]
64	Lei Wang	[116]
65	Xinmu Wang	[109] [110] [113] [114] [117]
66	Daniel J. Weyer	[101]
67	Francis G. Wolff	[76] [88] [90] [99] [100] [101] [113]
68	Xinmiao Zhang	[105]
69	Yu Zhou	[56] [68] [74] [82] [101]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page