Dilip K. Bhavsar

	2011
22		Dilip K. Bhavsar, Steve Poehlman: Test access and the testability features of the Poulson multi-core Intel Itanium® processor. ITC 2011: 1-8
21		Dilip K. Bhavsar: Harmony Widget for X-free scan testing. VTS 2011: 225-228
	2005
20		Dilip K. Bhavsar: A Built-in Self-Test Method for Write-only Content Addressable Memories. VTS 2005: 9-14
	2003
19		Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies: Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. ICCD 2003: 180-186
18		Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies: Testability Features of the Alpha 21364 Microprocessor. ITC 2003: 764-772
	2002
17		Dilip K. Bhavsar, Richard A. Davies: Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. VTS 2002: 16-24
	2001
16		Dilip K. Bhavsar, Rishan Tan: Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. VLSI Design 2001: 385-390
15		Dilip K. Bhavsar: Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. VTS 2001: 94-101
	2000
14		Dilip K. Bhavsar: Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability. IEEE Design & Test of Computers 17(2): 94-99 (2000)
	1999
13		Dilip K. Bhavsar: An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. ITC 1999: 311-318
12		Dilip K. Bhavsar: ITC 99 Panels. IEEE Design & Test of Computers 16(4): 96-99 (1999)
	1998
11		Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson: Testability access of the high speed test features in the Alpha 21264 microprocessor. ITC 1998: 487-495
10		Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill: A highly testable and diagnosable fabrication process test chip. ITC 1998: 853-861
9		Dilip K. Bhavsar, Yervant Zorian: ITC 97 Panel Sessions. IEEE Design & Test of Computers 15(1): 7, 91 (1998)
	1997
8		Dilip K. Bhavsar, John H. Edmondson: Alpha 21164 Testability Strategy. IEEE Design & Test of Computers 14(1): 25-33 (1997)
	1994
7		Dilip K. Bhavsar, John H. Edmondson: Testability Strategy of the ALPHA AXP 21164 Microprocessor. ITC 1994: 50-59
	1991
6		Dilip K. Bhavsar: An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes. ITC 1991: 768-776
5		Dilip K. Bhavsar: Testing Interconnections to Static RAMs. IEEE Design & Test of Computers 8(2): 63-71 (1991)
	1985
4		Dilip K. Bhavsar: "Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test. ITC 1985: 88-93
	1984
3		Dilip K. Bhavsar, Balakrishnan Krishnamurthy: Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? ITC 1984: 134-139
	1983
2		Dilip K. Bhavsar: Design For Test Calculus: An algorithm for DFT rules checking. DAC 1983: 300-307
	1981
1		Dilip K. Bhavsar, Richard W. Heckelman: Self-Testing by Polynomial Division. ITC 1981: 208-216

Coauthor Index

1	David R. Akeson	[10] [11]
2	Vijay Bettada	[19]
3	William J. Bowhill	[10]
4	Richard A. Davies	[17] [18] [19]
5	Ugonna Echeruo	[10]
6	John H. Edmondson	[7] [8]
7	Scott Erlanger	[18]
8	Michael K. Gowan	[11]
9	Joel Grodstein	[19]
10	Richard W. Heckelman	[1]
11	Daniel B. Jackson	[11]
12	Balakrishnan Krishnamurthy	[3]
13	Steve Poehlman	[22]
14	Rishan Tan	[16]
15	Yervant Zorian	[9]

Colors in the list of coauthors

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