Subhrajit Bhattacharya

	2011
24		Subhrajit Bhattacharya, Hordur Kristinn Heidarsson, Gaurav S. Sukhatme, Vijay Kumar: Cooperative control of autonomous surface vehicles for oil skimming and cleanup. ICRA 2011: 2374-2379
23		Subhrajit Bhattacharya, Maxim Likhachev, Vijay Kumar: Identification and Representation of Homotopy Classes of Trajectories for Search-based Path Planning in 3D. Robotics: Science and Systems 2011
	2010
22		Subhrajit Bhattacharya: Search-Based Path Planning with Homotopy Class Constraints. AAAI 2010
21		Subhrajit Bhattacharya, Maxim Likhachev, Vijay Kumar: Multi-agent path planning with multiple tasks and distance constraints. ICRA 2010: 953-959
20		Subhrajit Bhattacharya, Vijay Kumar, Maxim Likhachev: Distributed Optimization with Pairwise Constraints and its Application to Multi-robot Path Planning. Robotics: Science and Systems 2010
19		Subhrajit Bhattacharya, Vijay Kumar, Maxim Likhachev: Search-Based Path Planning with Homotopy Class Constraints. SOCS 2010
	2009
18		Paul Vernaza, Maxim Likhachev, Subhrajit Bhattacharya, Sachin Chitta, Aleksandr Kushleyev, Daniel D. Lee: Search-based planning for a legged robot over rough terrain. ICRA 2009: 2380-2387
	2005
17		Ruchir Puri, Leon Stok, Subhrajit Bhattacharya: Keeping hot chips cool. DAC 2005: 285-288
16		Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin: A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. ISQED 2005: 482-487
15		Martin Ohmacht, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Alan Gara, Mark Giampapa, Balaji Gopalsamy, Ruud A. Haring, Dirk Hoenicke, David J. Krolak, James A. Marcella, Ben J. Nathanson, Valentina Salapura, Michael E. Wazlowski: Blue Gene/L compute chip: Memory and Ethernet subsystem. IBM Journal of Research and Development 49(2-3): 255-264 (2005)
	2003
14		Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal: SEAS: a system for early analysis of SoCs. CODES+ISSS 2003: 150-155
	2002
13		John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 46(6): 691-708 (2002)
	2001
12		Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau: Automating the Design of SOCs Using Cores. IEEE Design & Test of Computers 18(5): 32-45 (2001)
	1999
11		Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya: Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466
	1998
10		Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama: Verification of RTL generated from scheduled behavior in a high-level synthesis flow. ICCAD 1998: 517-524
9		Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. ACM Trans. Design Autom. Electr. Syst. 3(2): 285-307 (1998)
	1997
8		Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta: An RTL methodology to enable low overhead combinational testing. ED&TC 1997: 146-152
7		Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey: H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. ITC 1997: 265-274
	1996
6		Subhrajit Bhattacharya, Sujit Dey: H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. VTS 1996: 74-80
5		Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Fast true delay estimation during high level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1088-1105 (1996)
	1994
4		Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Clock Period Optimization During Resource Sharing and Assignment. DAC 1994: 195-200
3		Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. DAC 1994: 491-496
2		Subhrajit Bhattacharya, Sujit Dey, Franc Brglez: Provably correct high-level timing analysis without path sensitization. ICCAD 1994: 736-742
	1993
1		Subhrajit Bhattacharya, Franc Brglez, Sujit Dey: Transformations and resynthesis for testability of RT-level control-data path specifications. IEEE Trans. VLSI Syst. 1(3): 304-318 (1993)

Coauthor Index

1	Toshiharu Asaka	[7]
2	Pranav Ashar	[10] [11]
3	Reinaldo A. Bergamaschi	[12] [13] [14] [15]
4	Daniel Brand	[13]
5	Franc Brglez	[1] [2] [3] [4] [5] [9]
6	Sachin Chitta	[18]
7	John A. Darringer	[13] [14] [16]
8	Jean-Marc Daveau	[12]
9	Sujit Dey	[1] [2] [3] [4] [5] [6] [7] [8] [9]
10	Nagu R. Dhanwada	[14]
11	William E. Dougherty	[14]
12	Colleen Fellenz	[12]
13	Alan Gara	[15]
14	Mark Giampapa	[15]
15	Balaji Gopalsamy	[15]
16	Aarti Gupta	[11]
17	Ruud A. Haring	[15]
18	Hordur Kristinn Heidarsson	[24]
19	Andreas Herkersdorf	[13]
20	Dirk Hoenicke	[15]
21	David J. Krolak	[15]
22	Vijay Kumar	[19] [20] [21] [23] [24]
23	Aleksandr Kushleyev	[18]
24	Daniel D. Lee	[18]
25	William R. Lee	[12]
26	Maxim Likhachev	[18] [19] [20] [21] [23]
27	James A. Marcella	[15]
28	Joseph K. Morrell	[13]
29	Michael Muhlada	[12]
30	Akira Mukaiyama	[10]
31	Indira Nair	[13] [14]
32	Ben J. Nathanson	[15]
33	Martin Ohmacht	[15]
34	Daniel L. Ostapko	[16]
35	Sarala Paliwal	[14]
36	Ruchir Puri	[17]
37	Anand Raghunathan	[10] [11]
38	Patricia Sagmeister	[13]
39	Valentina Salapura	[15]
40	Bhaskar Sengupta	[8]
41	Youngsoo Shin	[13] [14] [16]
42	Leon Stok	[17]
43	Gaurav S. Sukhatme (Gaurav Sukhatme)	[24]
44	Paul Vernaza	[18]
45	Ronoldo Wagner	[12]
46	Michael E. Wazlowski	[15]
47	Foster White	[12]
48	Masaaki Yoshida	[7]

Colors in the list of coauthors

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