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Koustav Bhattacharya Coauthor index pubzone.org

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14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRansford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan: Redundancy Mining for Soft Error Detection in Multicore Processors. IEEE Trans. Computers 60(8): 1114-1125 (2011)
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, N. Ranganathan: Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. IEEE Trans. VLSI Syst. 19(5): 918-923 (2011)
2010
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVenkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt: A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. IEEE Trans. VLSI Syst. 18(1): 29-38 (2010)
2009
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRansford Hyman Jr., Koustav Bhattacharya, N. Ranganathan: A Strategy for Soft Error Reduction in Multi Core Designs. ISCAS 2009: 2217-2220
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan: A VLSI System Architecture for Optical Flow Computation. ISCAS 2009: 357-360
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Nagarajan Ranganathan: A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED 2009: 388-393
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Nagarajan Ranganathan: A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. ISVLSI 2009: 91-96
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Nagarajan Ranganathan: RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design 2009: 453-458
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim: A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. IEEE Trans. VLSI Syst. 17(2): 194-206 (2009)
2008
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Nagarajan Ranganathan: A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI 2008: 273-278
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Nagarajan Ranganathan: Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED 2008: 99-104
2007
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan: Improving the reliability of on-chip L2 cache using redundancy. ICCD 2007: 224-229
2004
2no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJayanta Basak, Koustav Bhattacharya, Santanu Chaudhury: Multi Example Based Image Retrieval: An ICA Based Approach. ICVGIP 2004: 151-157
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoustav Bhattacharya, Santanu Chaudhury, Jayanta Basak: Video Summarization: A Machine Learning Based Approach. ICVGIP 2004: 429-434

Coauthor Index

1Jayanta Basak [1] [2]
2Hari Chakravarthula [12]
3Santanu Chaudhury [1] [2]
4Ransford Hyman Jr. [11] [14]
5Soontae Kim [3] [6]
6Venkataraman Mahalingam [10] [12]
7Robin R. Murphy [12]
8Kevin S. Pratt [12]
9N. Ranganathan (Nagarajan Ranganathan) [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]

Colors in the list of coauthors

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