Debashis Bhattacharya

	2005
21		Rob Roy, Debashis Bhattacharya, Vamsi Boppana: Transistor-Level Optimization of Digital Designs with Flex Cells. IEEE Computer 38(2): 53-61 (2005)
	1999
20		Debashis Bhattacharya: Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller. VTS 1999: 467-472
	1998
19		Debashis Bhattacharya: Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. VTS 1998: 8-14
	1997
18		Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya: Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. ICCAD 1997: 120-125
17		Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya: Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. VLSI Design 1997: 174-178
16		Debashis Bhattacharya, S. Freeman, W. Lin: Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. VLSI Design 1997: 289-296
15		Debashis Bhattacharya, Satyabroto Sinha: Invariance of stereo images via the theory of complex moments. Pattern Recognition 30(9): 1373-1386 (1997)
	1995
14		Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal: Test Generation for Path Delay Faults Using Binary Decision Diagrams. IEEE Trans. Computers 44(3): 434-447 (1995)
13		Ted Stanion, Debashis Bhattacharya, Carl Sechen: An efficient method for generating exhaustive test sets. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1516-1525 (1995)
12		Shang-E Tai, Debashis Bhattacharya: A three-stage partial scan design method to ease ATPG. J. Electronic Testing 7(1-2): 95-104 (1995)
	1994
11		Shang-E Tai, Debashis Bhattacharya: A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. VLSI Design 1994: 101-106
	1993
10		Debashis Bhattacharya, Prathima Agrawal: Boolean algebraic test generation using a distributed system. ICCAD 1993: 440-443
9		Shang-E Tai, Debashis Bhattacharya: Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. ICCD 1993: 564-567
8		Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal: Architecture of a Min-Max Simulator on MARS. VLSI Design 1993: 246-249
	1992
7		Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal: Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. DAC 1992: 159-164
	1991
6		Ted Stanion, Debashis Bhattacharya: TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation. FTCS 1991: 36-43
	1990
5		Debashis Bhattacharya: Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer. ISMVL 1990: 174-180
4		Ajit Agrawal, Debashis Bhattacharya: CMP3F: a high speed fault simulator for the Connection Machine. ITC 1990: 410-416
3		Debashis Bhattacharya, John P. Hayes: Designing for high-level test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 752-766 (1990)
2		Debashis Bhattacharya, John P. Hayes: A hierarchical test generation methodology for digital circuits. J. Electronic Testing 1(2): 103-123 (1990)
	1989
1		Debashis Bhattacharya, Brian T. Murray, John P. Hayes: High-Level Test Generation for VLSI. IEEE Computer 22(4): 16-24 (1989)

Coauthor Index

1	Ajit Agrawal	[4]
2	Prathima Agrawal	[7] [8] [10] [14]
3	Vishwani D. Agrawal	[7] [14]
4	Vamsi Boppana	[21]
5	S. Freeman	[16]
6	John P. Hayes	[1] [2] [3]
7	Kumar N. Lalgudi	[8]
8	W. Lin	[16]
9	Brian T. Murray	[1]
10	Kaushik Roy	[17] [18]
11	Rob Roy	[21]
12	Naushik Sankarayya	[17] [18]
13	Carl Sechen	[13]
14	Satyabroto Sinha	[15]
15	Ted Stanion	[6] [13]
16	Shang-E Tai	[9] [11] [12]

Colors in the list of coauthors

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