Sandeep Bhatia

	2010
14		Sandeep Bhatia: Low power compression architecture. VTS 2010: 183-187
13		Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki: Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Transactions 93-D(1): 17-23 (2010)
	2009
12		Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller: CTL and Its Usage in the EDA Industry. IEEE Design & Test of Computers 26(1): 36-43 (2009)
	2008
11		Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam: A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. VLSI Design 2008: 187-193
	2003
10		Sandeep Bhatia: Test Compaction by Using Linear-Matrix Driven Scan Chains. DFT 2003: 185-190
	1998
9		Prab Varma, Sandeep Bhatia: A structured test re-use methodology for core-based system chips. ITC 1998: 294-302
8		Sandeep Bhatia, Niraj K. Jha: Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. IEEE Trans. VLSI Syst. 6(4): 608-619 (1998)
	1997
7		Sandeep Bhatia, Prab Varma: Test Compaction in a Parallel Access Scan Environment. Asian Test Symposium 1997: 300-305
	1996
6		Sandeep Bhatia, Tushar Gheewala, Prab Varma: A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC 1996: 639-648
5		Sandeep Bhatia, Niraj K. Jha: Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 228-243 (1996)
	1994
4		Sandeep Bhatia, Niraj K. Jha: Genesis: A Behavioral Synthesis System for Hierarchical Testability. EDAC-ETC-EUROASIC 1994: 272-276
3		Sandeep Bhatia, Niraj K. Jha: Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. ICCD 1994: 91-96
	1993
2		Sandeep Bhatia, Niraj K. Jha: Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. ICCD 1993: 151-154
1		Sandeep Bhatia, Niraj K. Jha: Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. VLSI Design 1993: 275-280

Coauthor Index

1	Masayuki Arai	[13]
2	Thomas Bartenstein	[13]
3	Nilabha Dev	[11]
4	Brian Foutz	[13]
5	Sue Genova	[11]
6	Tushar Gheewala	[6]
7	Kazuhiko Iwasaki	[13]
8	Niraj K. Jha	[1] [2] [3] [4] [5] [8]
9	Vinayak Kadam	[11]
10	Rohit Kapur	[12]
11	Brion L. Keller	[12] [13]
12	Subhasish Mukherjee	[11]
13	Paul Reuter	[12]
14	Anis Uzzaman	[13]
15	Prab Varma	[6] [7] [9]

Colors in the list of coauthors

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