Navakanta Bhat

	2012
23		M. Pramod, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy: CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy. VLSI Design 2012: 173-178
	2011
22		Siva Rama Krishna V., Bharadwaj Amrutur, Navakanta Bhat, Chakra Pani K., Sampath Srinivasan: Detection of Glycated Hemoglobin using 3-Aminophenylboronic Acid Modified Graphene Oxide. BIODEVICES 2011: 109-113
21		Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat: Power Scalable Digital Baseband Architecture for IEEE 802.15.4. VLSI Design 2011: 30-35
20		Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur: Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. IEEE Trans. VLSI Syst. 19(2): 295-304 (2011)
	2009
19		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS Circuits. ISCAS 2009: 2309-2312
18		Balaji Jayaraman, Navakanta Bhat: Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology. J. Low Power Electronics 5(4): 484-496 (2009)
	2008
17		Rakesh Gnana David Jeyasingh, Navakanta Bhat: A low power, process invariant keeper for high speed dynamic logic circuits. ISCAS 2008: 1668-1671
16		Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat: Optimal power and noise allocation for analog and digital sections of a low power radio receiver. ISLPED 2008: 271-276
15		Sukumar Jairam, Navakanta Bhat: GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes. VLSI Design 2008: 589-594
14		R. Srinivasan, Navakanta Bhat: Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance. J. Low Power Electronics 4(2): 240-246 (2008)
13		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Hybrid-CV Modeling for Estimating the Variability in Dynamic Power. J. Low Power Electronics 4(3): 263-274 (2008)
	2007
12		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. ICCTA 2007: 94-98
11		Balaji Jayaraman, Navakanta Bhat: High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOS. ISCAS 2007: 3071-3074
10		Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar: Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis. VLSI-SoC 2007: 280-283
9		B. P. Harish, Navakanta Bhat, Mahesh B. Patil: On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 606-614 (2007)
	2005
8		R. Srinivasan, Navakanta Bhat: Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications. VLSI Design 2005: 392-396
	2004
7		H. C. Srinivasaiah, Navakanta Bhat: Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. VLSI Design 2004: 285-290
6		Sukumar Jairam, C. Venkatesh, Navakanta Bhat, Shyam Singh, Rudra Pratap: A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework. VLSI Design 2004: 642-645
	2003
5		R. Srinivasan, Navakanta Bhat: Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's. VLSI Design 2003: 105-109
4		H. C. Srinivasaiah, Navakanta Bhat: Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 742-747 (2003)
3		C. Venkatesh, Shashidhar Pati, Navakanta Bhat: Torsional Mems Varactor With Low Actuation Voltage. International Journal of Computational Engineering Science 4(3): 555-558 (2003)
2		Shashidhar Pati, C. Venkatesh, Navakanta Bhat, Rudra Pratap: Voltage Controlled Oscillator Using Tunable Mems Resonator. International Journal of Computational Engineering Science 4(3): 675-678 (2003)
	2002
1		H. C. Srinivasaiah, Navakanta Bhat: Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. VLSI Design 2002: 225-

Coauthor Index

1	Bharadwaj S. Amrutur (Bharadwaj Amrutur)	[16] [20] [21] [22] [23]
2	Gaurab Banerjee	[23]
3	K. N. Bhat	[23]
4	Satyam Dwivedi	[16] [21]
5	B. P. Harish	[9] [12] [13] [19]
6	Sukumar Jairam	[6] [15]
7	Balaji Jayaraman	[11] [18]
8	Rakesh Gnana David Jeyasingh	[17] [20]
9	Chakra Pani K.	[22]
10	Chaitanya Kshirsagar	[10]
11	Shashidhar Pati	[2] [3]
12	Mahesh B. Patil	[9] [12] [13] [19]
13	M. Pramod	[23]
14	Rudra Pratap	[2] [6]
15	Praveen C. Ramamurthy	[23]
16	Urmimala Roy	[10]
17	Manodipan Sahoo	[16]
18	Kannan Aryaperumal Sankaragomathi	[16]
19	Chandan Kumar Sarkar	[10]
20	Srimoyee Sen	[10]
21	Shyam Singh	[6]
22	H. C. Srinivasaiah	[1] [4] [7]
23	R. Srinivasan	[5] [8] [14]
24	Sampath Srinivasan	[22]
25	Siva Rama Krishna V.	[22]
26	C. Venkatesh	[2] [3] [6]

Colors in the list of coauthors

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