Sanjukta Bhanja

	2011
30		Sanjukta Bhanja, Javier F. Pulecio: A review of magnetic cellular automata systems. ISCAS 2011: 2373-2376
29		Saket Srivastava, Arjun Asthana, Sanjukta Bhanja, Sudeep Sarkar: QCAPro - An error-power estimation tool for QCA circuit design. ISCAS 2011: 2377-2380
28		Jayita Das, Syed M. Alam, Srinath Rajaram, Sanjukta Bhanja: Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices CoRR abs/1102.4034: (2011)
27		Anita Kumari, Sanjukta Bhanja: Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays. IEEE Trans. VLSI Syst. 19(4): 714-717 (2011)
26		Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja: Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. Microelectronics Reliability 51(2): 485-501 (2011)
	2009
25		Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 ACM 2009
24		Anita Kumari, Javier F. Pulecio, Sanjukta Bhanja: Defect characterization in magnetic field coupled arrays. ISQED 2009: 436-441
23		Karthikeyan Lingasubramanian, Sanjukta Bhanja: An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. VLSI Design 2009: 485-490
22		Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja: Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis CoRR abs/0906.3282: (2009)
21		Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja: Probabilistic Error Modeling for Nano-Domain Logic Circuits. IEEE Trans. VLSI Syst. 17(1): 55-65 (2009)
	2008
20		Vijaykrishnan Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008 ACM 2008
19		Saket Srivastava, Sanjukta Bhanja: Integrating a Nanologic Knowledge Module Into an Undergraduate Logic Design Course. IEEE Trans. Education 51(3): 349-355 (2008)
18		Sanjukta Bhanja, Sudeep Sarkar: Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits. IEEE Trans. VLSI Syst. 16(5): 528-541 (2008)
	2007
17		Karthikeyan Lingasubramanian, Sanjukta Bhanja: Probabilistic maximum error modeling for unreliable logic circuits. ACM Great Lakes Symposium on VLSI 2007: 223-226
16		Saket Srivastava, Sanjukta Bhanja: Hierarchical Probabilistic Macromodeling for QCA Circuits. IEEE Trans. Computers 56(2): 174-190 (2007)
15		Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli: QCA Circuits for Robust Coplanar Crossing. J. Electronic Testing 23(2-3): 193-210 (2007)
	2006
14		Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli: Novel designs for thermally robust coplanar crossing in QCA. DATE 2006: 786-791
13		Thara Rejimon, Sanjukta Bhanja: Wide Limited Switch Dynamic Logic Circuit Implementations. VLSI Design 2006: 94-99
12		Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006)
11		Thara Rejimon, Sanjukta Bhanja: A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. IEEE Trans. VLSI Syst. 14(10): 1130-1139 (2006)
	2005
10		Nirmal Ramalingam, Sanjukta Bhanja: Causal probabilistic input dependency learning for switching model in VLSI circuits. ACM Great Lakes Symposium on VLSI 2005: 112-115
9		Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591
8		Thara Rejimon, Sanjukta Bhanja: An Accurate Probalistic Model for Error Detection. VLSI Design 2005: 717-722
	2004
7		Shiva Shankar Ramani, Sanjukta Bhanja: Any-time probabilistic switching model using bayesian networks. ISLPED 2004: 86-89
6		Sanjukta Bhanja, N. Ranganathan: Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. VLSI Syst. 12(12): 1360-1370 (2004)
	2003
5		Sanjukta Bhanja, N. Ranganathan: Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. VLSI Syst. 11(4): 558-567 (2003)
	2002
4		Sanjukta Bhanja, N. Ranganathan: Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD 2002: 388-390
3		Sanjukta Bhanja, N. Ranganathan: Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. VLSI Design 2002: 187-192
	2001
2		Sanjukta Bhanja, N. Ranganathan: Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC 2001: 209-214
	1998
1		Sanjukta Bhanja, Lynn M. Fletcher-Heath, Lawrence O. Hall, Dmitry B. Goldgof, Jeffrey P. Krischer: A Qualitative Expert System for Clinical Trial Assignment. FLAIRS Conference 1998: 84-88

Coauthor Index

1	Syed M. Alam	[22] [26] [28]
2	Arjun Asthana	[29]
3	R. Iris Bahar	[25]
4	Jayita Das	[28]
5	Lynn M. Fletcher-Heath	[1]
6	Dmitry B. Goldgof	[1]
7	Lawrence O. Hall	[1]
8	Jeffrey P. Krischer	[1]
9	Anita Kumari	[24] [27]
10	Karthikeyan Lingasubramanian	[9] [12] [17] [21] [22] [23] [26]
11	Fabrizio Lombardi	[14] [15] [25]
12	Enrico Macii	[20]
13	Yehia Massoud	[25]
14	Marco Ottavi	[14] [15]
15	Salvatore Pontarelli	[14] [15]
16	Javier F. Pulecio	[24] [30]
17	Srinath Rajaram	[28]
18	Nirmal Ramalingam	[10]
19	Shiva Shankar Ramani	[7]
20	N. Ranganathan (Nagarajan Ranganathan)	[2] [3] [4] [5] [6] [9] [12]
21	Thara Rejimon	[8] [11] [13] [21]
22	Sudeep Sarkar	[18] [29]
23	Saket Srivastava	[16] [19] [29]
24	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[20]
25	Zhiyuan Yan	[20]

Colors in the list of coauthors

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