Jayanta Bhadra

Jay Bhadra

	2012
38		Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra: An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. ASP-DAC 2012: 163-168
	2011
37		Magdy S. Abadir, Jay Bhadra, Li-C. Wang: 12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011 IEEE 2011
36		Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula: A Unified Formal Framework for Analyzing Functional and Speed-path Properties. MTV 2011: 44-45
	2010
35		Magdy S. Abadir, Jay Bhadra, Li-C. Wang: 11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010 IEEE 2010
34		Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronald Syzdek: Modeling and verification of industrial flash memories. ISQED 2010: 705-712
33		Po-Hsien Chang, Li-C. Wang, Jayanta Bhadra: A kernel-based approach for functional test program generation. ITC 2010: 164-173
32		Sandip Ray, Jayanta Bhadra: Innovative practices session 7C: Verification and testing challenges in high-level synthesis. VTS 2010: 250
	2009
31		Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra: Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI 2009: 339-344
30		Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra: On soft error rate analysis of scaled CMOS designs - A statistical perspective. ICCAD 2009: 157-163
29		Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller: An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. ISQED 2009: 377-381
28		Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra: Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. ISVLSI 2009: 241-246
27		Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, Jayanta Bhadra: Portable simulation/emulation stimulus on an industrial-strength SoC. ITC 2009: 1
26		Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra: Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. ITC 2009: 1-8
25		Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra: Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. MTV 2009: 3-8
	2008
24		Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir: Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. IEEE Trans. VLSI Syst. 16(4): 388-396 (2008)
	2007
23		Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA IEEE Computer Society 2007
22		Sandip Ray, Jayanta Bhadra: A Mechanized Refinement Framework for Analysis of Custom Memories. FMCAD 2007: 239-242
21		Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra: An incremental learning framework for estimating signal controllability in unit-level verification. ICCAD 2007: 250-257
20		Onur Guzey, Li-C. Wang, Jayanta Bhadra: Enhancing signal controllability in functional test-benches through automatic constraint extraction. ITC 2007: 1-10
19		Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang: Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Design & Test of Computers 24(2): 110-111 (2007)
18		Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray: A Survey of Hybrid Techniques for Functional Verification. IEEE Design & Test of Computers 24(2): 112-122 (2007)
	2006
17		Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA IEEE Computer Society 2006
16		Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir: Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36
	2005
15		Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova: Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV 2005: 111-118
14		Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham: A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. Formal Methods in System Design 27(1-2): 67-112 (2005)
	2004
13		Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra: Formal Verification of a System-on-Chip Using Computation Slicing. ITC 2004: 810-819
12		Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115-
11		Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Design & Test of Computers 21(6): 494-502 (2004)
	2003
10		Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV 2003: 32-37
9		Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra: Model Checking of Security Protocols with Pre-configuration. WISA 2003: 1-15
8		Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri: A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electronic Testing 19(2): 149-160 (2003)
	2002
7		Jayanta Bhadra, Narayanan Krishnamurthy: Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. ITC 2002: 213-222
6		Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra: Program Slicing for Hierarchical Test Generation. VTS 2002: 237-246
5		Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280
	2001
4		Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402
3		Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham: Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519
	2000
2		Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Automatic Validation Test Generation Using Extracted Control Models. VLSI Design 2000: 312-
	1999
1		Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Improving Witness Search Using Orders on States. ICCD 1999: 452-457

Coauthor Index

1	Magdy S. Abadir	[3] [4] [5] [10] [11] [12] [15] [16] [17] [18] [19] [23] [24] [35] [37]
2	Jacob A. Abraham	[1] [2] [3] [4] [5] [6] [8] [9] [12] [13] [14]
3	Mrinal Bose	[25] [27] [28] [29] [31]
4	David Burgess	[15]
5	Hui-Ling Chan	[38]
6	Chia-Ching Chang	[38]
7	Chia-Ling Chang	[26] [38]
8	Po-Hsien Chang	[33]
9	Vijay K. Garg	[13]
10	Onur Guzey	[20]
11	Kyoil Kim	[9]
12	Heon-Mo Koo	[16]
13	Narayanan Krishnamurthy	[5] [7] [10] [11] [12]
14	Atabak Mahram	[28]
15	Andrew K. Martin	[4] [14]
16	Hillel Miller	[29]
17	Prabhat Mishra	[16]
18	Prashant Naphade	[29]
19	Oswaldo Olivo	[36]
20	Huan-Kai Peng	[30]
21	Thomas Portlock	[34]
22	Wei Qin	[25] [28] [31]
23	Sandip Ray	[18] [22] [32] [34] [36]
24	Javier Ruiz	[27]
25	Alper Sen	[13]
26	Rohit Srivastava	[27]
27	Robert W. Sumners (Rob Sumners)	[1] [2]
28	Ronald Syzdek	[34]
29	Francisco Torres	[27]
30	Ekaterina Trofimova	[15] [24]
31	Raghuram S. Tupuri	[8]
32	Vivekananda M. Vedula	[6] [8] [36]
33	Vyas Venkataraman	[25] [28] [31]
34	Di Wang	[25] [28] [31]
35	Hangsheng Wang	[31]
36	Li-C. Wang	[17] [18] [19] [20] [21] [23] [33] [35] [37]
37	Zhen Wang	[31]
38	Charles H.-P. Wen	[21] [26] [27] [30] [38]
39	Jing Zeng	[3]

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page