V. S. Kanchana Bhaaskaran

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2010

3 V. S. Kanchana Bhaaskaran, J. P. Raina: Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits. Journal of Circuits, Systems, and Computers 19(2): 335-347 (2010)

2008

2 V. S. Kanchana Bhaaskaran, J. P. Raina: Differential Cascode Adiabatic Logic Structure for Low Power. J. Low Power Electronics 4(2): 178-190 (2008)

2006

1 V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel: Semi-Custom Design of Adiabatic Adder Circuits. VLSI Design 2006: 745-748

	2010
3		V. S. Kanchana Bhaaskaran, J. P. Raina: Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits. Journal of Circuits, Systems, and Computers 19(2): 335-347 (2010)
	2008
2		V. S. Kanchana Bhaaskaran, J. P. Raina: Differential Cascode Adiabatic Logic Structure for Low Power. J. Low Power Electronics 4(2): 178-190 (2008)
	2006
1		V. S. Kanchana Bhaaskaran, S. Salivahanan, D. S. Emmanuel: Semi-Custom Design of Adiabatic Adder Circuits. VLSI Design 2006: 745-748

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