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| 2012 | ||
|---|---|---|
| 11 | Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Chris Madden, Keisuke Saito, Koji Sano, Vinod Murugan, Wendemagegnehu T. Beyene, Ken Chang, Chuck Yuan: A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration. ISSCC 2012: 132-134 | |
| 10 | Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris Madden, Ken Chang, Chuck Yuan: A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link. ISSCC 2012: 138-140 | |
| 9 | Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan: A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. J. Solid-State Circuits 47(4): 911-925 (2012) | |
| 8 | Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan: A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. J. Solid-State Circuits 47(4): 926-937 (2012) | |
| 2007 | ||
| 7 | Wai-Yeung Yip, Scott Best, Wendemagegnehu T. Beyene, Ralf Schmitt: System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production. ASP-DAC 2007: 858-865 | |
| 6 | Wendemagegnehu T. Beyene: Low-Order Rational Approximation of Interconnects Using Neural-Network Based Pole-Clustering Techniques. ISCAS 2007: 1501-1504 | |
| 5 | Wendemagegnehu T. Beyene: Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 166-176 (2007) | |
| 2003 | ||
| 4 | Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim, Madhavan Swaminathan: Modeling and Analysis of Power Distribution Networks for Gigabit Applications. ISQED 2003: 235-240 | |
| 3 | Jinwoo Choi, Sung-Hwan Min, Joong-Ho Kim, Madhavan Swaminathan, Wendemagegnehu T. Beyene, Chuck Yuan: Modeling and Analysis of Power Distribution Networks for Gigabit Applications. IEEE Trans. Mob. Comput. 2(4): 299-313 (2003) | |
| 2002 | ||
| 2 | Wendemagegnehu T. Beyene, Chuck Yuan: On the Use of Windows for Accurate Analysis of Package Interconnects. ISQED 2002: 181- | |
| 1997 | ||
| 1 | Wendemagegnehu T. Beyene, José E. Schutt-Ainé: Transient analysis of diode switching circuits using asymptotic waveform evaluation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1447-1453 (1997) | |
Colors in the list of coauthors
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