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Vaughn Betz Coauthor index pubzone.org

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DBLP keys2012
25Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWei Zhang, Vaughn Betz, Jonathan Rose: Portable and scalable FPGA-based acceleration of a direct linear system solver. TRETS 5(1): 6 (2012)
2011
24Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHenry Wong, Vaughn Betz, Jonathan Rose: Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. FPGA 2011: 5-14
23Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAdrian Ludwin, Vaughn Betz: Efficient and Deterministic Parallel Placement for FPGAs. ACM Trans. Design Autom. Electr. Syst. 16(3): 22 (2011)
22Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz: FPGAs, Programming Models, and Kit Cars. IEEE Design & Test of Computers 28(4): 112 (2011)
2010
21no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Stephen Brown: Recent FPGA Advances and Challenges. ERSA 2010: 117-120
20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDoris Chen, Deshanand Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz: A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA 2010: 167-176
2009
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz: FPGA challenges and opportunities at 40nm and beyond. FPL 2009: 4
2008
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAdrian Ludwin, Vaughn Betz, Ketan Padalia: High-quality, deterministic parallel placement for FPGAs on commodity hardware. FPGA 2008: 14-23
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRyan Fung, Vaughn Betz, William Chow: Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 686-697 (2008)
2007
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRussell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy: Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 278-290 (2007)
2006
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRussell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy: Power-aware RAM mapping for FPGA embedded memory blocks. FPGA 2006: 189-198
2005
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDavid M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20
2004
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRyan Fung, Vaughn Betz, William Chow: Simultaneous short-path and long-path timing optimization for FPGAs. ICCAD 2004: 838-845
2003
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDavid M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose: The StratixTM routing and logic architecture. FPGA 2003: 12-20
2000
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Jonathan Rose: Automatic generation of FPGA routing architectures from high-level descriptions. FPGA 2000: 175-184
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAlexander Marquardt, Vaughn Betz, Jonathan Rose: Timing-driven placement for FPGAs. FPGA 2000: 203-213
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAlexander Marquardt, Vaughn Betz, Jonathan Rose: Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. VLSI Syst. 8(1): 84-93 (2000)
1999
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAlexander Marquardt, Vaughn Betz, Jonathan Rose: Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. FPGA 1999: 37-46
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Jonathan Rose: FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. FPGA 1999: 59-68
1998
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJordan S. Swartz, Vaughn Betz, Jonathan Rose: A Fast Routability-Driven Router for FPGAs. FPGA 1998: 140-149
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Jonathan Rose: How Much Logic Should Go in an FPGA Logic Block? IEEE Design & Test of Computers 15(1): 10-15 (1998)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Jonathan Rose: Effect of the prefabricated routing track distribution on FPGA area-efficiency. IEEE Trans. VLSI Syst. 6(3): 445-456 (1998)
1997
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Jonathan Rose: VPR: A new packing, placement and routing tool for FPGA research. FPL 1997: 213-222
1996
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Jonathan Rose: Directional bias and non-uniformity in FPGA global routing architectures. ICCAD 1996: 652-659
1995
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVaughn Betz, Jonathan Rose: Using Architectural ``Families'' to Increase FPGA Speed and Density. FPGA 1995: 10-16

Coauthor Index

1Elias Ahmed [14]
2Gregg Baeckler [14]
3Mark Bourgeault [14]
4Stephen Brown [21]
5David Cashman [14]
6Doris Chen [20]
7William Chow [13] [17]
8Jeffrey Chromczak [20]
9Richard Cliff [12] [14]
10Aaron Egier [16]
11Ryan Fung [13] [17] [20]
12David R. Galloway [14]
13Thiagaraja Gopalsamy [15] [16]
14Michael Hutton (Michael D. Hutton, Mike Hutton) [14]
15David Jefferson [12]
16Christopher Lane [12] [14]
17Andy Lee [12] [14]
18Paul Leventis [12] [14]
19David M. Lewis [12] [14] [20]
20Adrian Ludwin [18] [23]
21Alexander Marquardt [8] [9] [10]
22Sandy Marquardt [12] [14]
23Cameron McClintock [12] [14]
24David Neto [15] [16] [20]
25Ketan Padalia [14] [18]
26Bruce Pedersen [12] [14]
27Giles Powell [12] [14]
28Boris Ratchev [14]
29Srinivas Reddy [12] [14]
30Jonathan Rose [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [24] [25]
31Jay Schleicher [14]
32Deshanand Singh [20]
33Kevin Stevens [14]
34Jordan S. Swartz [6]
35Russell Tessier [15] [16]
36Henry Wong [24]
37Chris Wysocki [12]
38Richard Yuan [14]
39Wei Zhang [25]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page