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Yves Berviller Coauthor index pubzone.org

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DBLP keys2011
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMichael Guarisco, Eric Dabellani, Nicolas Marques, Hassan Rabah, Yves Berviller, Serge Weber: An efficient VLSI implementation of H.264/AVC intra-frame transcoder. ICECS 2011: 1-4
2010
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAfandi Ahmad, Abbes Amira, Michael Guarisco, Hassan Rabah, Yves Berviller: Efficient implementation of a 3-D medical imaging compression system using CAVLC. ICIP 2010: 3773-3776
2009
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMichael Guarisco, Hassan Rabah, Yves Berviller, Serge Weber, Said Belkouch: FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. SoCC 2009: 423-426
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCamel Tanougast, Michael Janiaut, Yves Berviller, Hassan Rabah, Serge Weber, Ahmed Bouridane: An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis. IEEE Trans. Circuits Syst. Video Techn. 19(2): 237-249 (2009)
2007
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOscar Pérez, Yves Berviller, Camel Tanougast, Serge Weber: The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation. J. UCS 13(3): 349-362 (2007)
2005
9no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMichael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber: Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. FPL 2005: 386-390
2004
8no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChristian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber: FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T. ESA/VLSI 2004: 606-610
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLChristian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber: FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. FPL 2004: 1027-1031
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCamel Tanougast, Yves Berviller, Christian Mannino, Hassan Rabah, Michael Janiaut, Serge Weber: SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation. IEEE International Workshop on Rapid System Prototyping 2004: 157-163
2003
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCamel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber: Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design. IPDPS 2003: 178
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPhilippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber: Hardware Partitioning Software for Dynamically Reconfigurable SoC Design. IWSOC 2003: 106-111
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCamel Tanougast, Yves Berviller, Serge Weber, Philippe Brunet: A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems. EURASIP J. Adv. Sig. Proc. 2003(6): 494-501 (2003)
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCamel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber, Hassan Rabah: Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. Microprocessors and Microsystems 27(3): 115-130 (2003)
2000
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCamel Tanougast, Yves Berviller, Serge Weber: Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation. IPDPS Workshops 2000: 959-965

Coauthor Index

1Afandi Ahmad [13]
2Abbes Amira [13]
3Said Belkouch [12]
4Ahmed Bouridane [11]
5Philippe Brunet [2] [3] [4] [5]
6Eric Dabellani [14]
7Michael Guarisco [12] [13] [14]
8Michael Janiaut [6] [7] [8] [9] [11]
9Christian Mannino [6] [7] [8] [9]
10Nicolas Marques [14]
11Oscar Pérez [10]
12Hassan Rabah [2] [6] [7] [8] [9] [11] [12] [13] [14]
13Camel Tanougast [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
14Serge Weber [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14]

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