Krzysztof S. Berezowski

	2012
11		Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava: Design of an RNS reverse converter for a new five-moduli special set. ACM Great Lakes Symposium on VLSI 2012: 67-70
	2011
10		Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava: Fast and energy-efficient constant-coefficient FIR filters using residue number system. ISLPED 2011: 385-390
9		Tejaswi Gowda, Sarma B. K. Vrudhula, N. Kulkarni, Krzysztof S. Berezowski: Identification of Threshold Functions and Synthesis of Threshold Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 665-677 (2011)
	2010
8		Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski: Out-of-order issue logic using sorting networks. ACM Great Lakes Symposium on VLSI 2010: 385-388
7		Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula: A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. ISVLSI 2010: 210-215
	2009
6		Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak: Exploiting residue number system for power-efficient digital signal processing in embedded processors. CASES 2009: 19-28
	2008
5		Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski: Analytical results for design space exploration of multi-core processors employing thread migration. ISLPED 2008: 229-232
	2007
4		Krzysztof S. Berezowski, Sarma B. K. Vrudhula: Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. ISMVL 2007: 24
3		Krzysztof S. Berezowski, Sarma B. K. Vrudhula: Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. Multiple-Valued Logic and Soft Computing 13(4-6): 447-466 (2007)
	2005
2		Krzysztof S. Berezowski, Sarma B. K. Vrudhula: Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. DSD 2005: 139-143
	2001
1		Krzysztof S. Berezowski: Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis. DSD 2001: 422-429

Coauthor Index

1	Janusz Biernat	[10] [11]
2	Gayathri Chalivendra	[7]
3	Rooju Chokshi	[6]
4	Lawrence T. Clark	[8]
5	Tejaswi Gowda	[9]
6	N. Kulkarni	[9]
7	Samuel Leshner	[7]
8	Satendra Kumar Maurya	[8]
9	Siddhesh S. Mhambrey	[8]
10	Saurabh Patel	[7]
11	Piotr Patronik	[10] [11]
12	Stanislaw J. Piestrak	[6] [10] [11]
13	Ravishankar Rao	[5]
14	Aviral Shrivastava	[6] [10] [11]
15	Sarma B. K. Vrudhula	[2] [3] [4] [5] [7] [9]
16	Xiaoyin Yao	[7]

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page