dblp.uni-trier.dewww.dagstuhl.dewww.uni-trier.de

Jacques Benkoski Coauthor index pubzone.org

List of publications from the DBLP Bibliography Server - FAQ
Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

DBLP keys2007
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJacques Benkoski, Michelle Clancy, Shankar Krishnamoorthy, David Holt, Ravi Subramanian, Clive Bittlestone, Tsuyoshi Yamamoto, Andrew Kanhg: Do Digital Design and Variability Mix like Oil and Water? ISQED 2007: 672-676
2002
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLK. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment: Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. DATE 2002: 538
2001
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLBill Alexander, Jacques Benkoski: 0.13 micron: Will the Speed Bumps Slow the Race to Market? ISQED 2001: 229-
2000
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRobert N. Blair, Jacques Benkoski: How Do You Select A High Quality EDA Tool Flow?. ISQED 2000: 17-
1991
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJacques Benkoski, Andrzej J. Strojwas: The Role of Timing Verification in Layout Synthesis. DAC 1991: 612-619
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRonald Stewart, Jacques Benkoski: Static Timing Analysis Using Interval Constraints. ICCAD 1991: 308-311
1990
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man: Timing verification using statically sensitizable paths. IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 10723-10784 (1990)
1989
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJacques Benkoski, Andrzej J. Strojwas: Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. DAC 1989: 668-673
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJacques Benkoski, Andrzej J. Strojwas: Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. ITC 1989: 153-160
1987
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJacques Benkoski, Andrzej J. Strojwas: A New Approach to Hierarchical and Statistical Timing Simulations. IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 1039-1052 (1987)

Coauthor Index

1Bill Alexander [8]
2Clive Bittlestone [10]
3Robert N. Blair [7]
4K. Brock [9]
5Luc J. M. Claesen [4]
6Michelle Clancy [10]
7Antun Domic [9]
8C. Edwards [9]
9David Holt [10]
10Andrew Kanhg [10]
11M. Kliment [9]
12Shankar Krishnamoorthy [10]
13R. Lannoo [9]
14Hugo De Man [4]
15E. Vanden Meersch [4]
16David Overhauser [9]
17Ulf Schlichtmann [9]
18Ronald Stewart [5]
19Andrzej J. Strojwas (Andreas J. Strojwas) [1] [2] [3] [6]
20Ravi Subramanian [10]
21Tsuyoshi Yamamoto [10]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page