Lionel Bening

	2001
5		Lionel Bening, Harry Foster: Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog. Kluwer 2001: I-XXIII, 1-281
4		Lionel Bening, Harry Foster: Optimizing Multiple EDA Tools within the ASIC Design Flow. IEEE Design & Test of Computers 18(4): 46-55 (2001)
	1999
3		Lionel Bening: A Two-State Methodology for RTL Logic Simulation. DAC 1999: 672-677
	1982
2		Lionel Bening, Thomas A. Lane, Curtis R. Alexander, James E. Smith: Developments in logic network path delay analysis. DAC 1982: 605-615
	1979
1		Lionel Bening: Developments in computer simulation of gate level physical logic. DAC 1979: 561-567

Coauthor Index

1	Curtis R. Alexander	[2]
2	Harry Foster	[4] [5]
3	Thomas A. Lane	[2]
4	James E. Smith	[2]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page