Wendy Belluomini

	2011
15		Jorge Guerra, Himabindu Pucha, Joseph S. Glider, Wendy Belluomini, Raju Rangaswami: Cost Effective Storage using Extent Based Dynamic Tiering. FAST 2011: 273-286
	2010
14		Pin Zhou, Binny Gill, Wendy Belluomini, Avani Wildani: GAUL: Gestalt Analysis of Unstructured Logs for Diagnosing Recurring Problems in Large Enterprise Storage Systems. SRDS 2010: 148-159
13		Jorge Guerra, Wendy Belluomini, Joseph S. Glider, Karan Gupta, Himabindu Pucha: Energy proportionality for storage: impact and feasibility. Operating Systems Review 44(1): 35-39 (2010)
	2009
12		Eric Rozier, Wendy Belluomini, Veera Deenadhayalan, Jim Hafner, K. K. Rao, Pin Zhou: Evaluating the impact of Undetected Disk Errors in RAID systems. DSN 2009: 83-92
	2008
11		James L. Hafner, Veera Deenadhayalan, Wendy Belluomini, Krishnakumar Rao: Undetected disk errors in RAID arrays. IBM Journal of Research and Development 52(4-5): 413-426 (2008)
10		Mohammad Banikazemi, Jim Hafner, Wendy Belluomini, K. K. Rao, Dan E. Poff, Bülent Abali: Flipstone: managing storage with fail-in-place and deferred maintenance service models. Operating Systems Review 42(1): 54-62 (2008)
	2006
9		Wendy Belluomini, Damir Jamsek, Andrew K. Martin, Chandler McDowell, Robert K. Montoye, Hung C. Ngo, Jun Sawada: Limited switch dynamic logic circuits for high-speed low-power circuit design. IBM Journal of Research and Development 50(2-3): 277-286 (2006)
	2004
8		Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka: A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480
	2001
7		Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng: Timed circuits: a new paradigm for high-speed design. ASP-DAC 2001: 335-340
6		Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Timed circuit verification using TEL structures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 129-146 (2001)
	2000
5		Wendy Belluomini, Chris J. Myers: Timed state space exploration using POSETs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 501-520 (2000)
	1999
4		Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC 1999: 3-12
3		Robert Thacker, Wendy Belluomini, Chris J. Myers: Timed Circuit Synthesis Using Implicit Methods. VLSI Design 1999: 181-188
	1998
2		Wendy Belluomini, Chris J. Myers: Verification of Timed Systems Using POSETs. CAV 1998: 403-415
	1997
1		Wendy Belluomini, Chris J. Myers: Efficient Timing Analysis Algorithms for Timed State Space Exploration. ASYNC 1997: 88-100

Coauthor Index

1	Bülent Abali	[10]
2	Jacob A. Abraham	[8]
3	Mohammad Banikazemi	[10]
4	Ramyanshu Datta	[8]
5	Veera Deenadhayalan	[11] [12]
6	Binny Gill	[14]
7	Joseph S. Glider	[13] [15]
8	Jorge Guerra	[13] [15]
9	Karan Gupta	[13]
10	James Lee Hafner (James L. Hafner)	[11]
11	Jim Hafner	[10] [12]
12	H. Peter Hofstee	[4] [6]
13	Damir Jamsek	[9]
14	Kip Kallpack	[7]
15	Jente B. Kuang	[8]
16	Andrew K. Martin	[9]
17	Chandler McDowell	[8] [9]
18	Robert K. Montoye	[8] [9]
19	Chris J. Myers	[1] [2] [3] [4] [5] [6] [7]
20	Hung C. Ngo	[8] [9]
21	Kevin J. Nowka	[8]
22	Eric Peskin	[7]
23	Dan E. Poff	[10]
24	Himabindu Pucha	[13] [15]
25	Raju Rangaswami	[15]
26	K. K. Rao	[10] [12]
27	Krishnakumar Rao	[11]
28	Eric Rozier	[12]
29	Jun Sawada	[9]
30	Robert Thacker	[3]
31	Avani Wildani	[14]
32	Hao Zheng (Hank Jayne)	[7]
33	Pin Zhou	[12] [14]

Colors in the list of coauthors

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