 | 2012 |
| 15 |  | Smriti Joshi,
Anne Lombardot,
Philippe Flatresse,
Carmelo D'agostino,
Andre Juge,
Edith Beigné,
Stéphane Girard:
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations.
J. Low Power Electronics 8(1): 113-124 (2012) |
| 2011 |
| 14 |  | Jean-Frédéric Christmann,
Edith Beigné,
Cyril Condemine,
Pascal Vivet,
Jérôme Willemin,
Nicolas Leblond,
Christian Piguet:
Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems.
IEEE Design & Test of Computers 28(5): 84-94 (2011) |
| 13 |  | Pascal Vivet,
Edith Beigné,
Hugo Lebreton,
Nacer-Eddine Zergainoh:
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling.
J. Low Power Electronics 7(2): 265-273 (2011) |
| 12 |  | Carolina Albea,
Diego Puschini,
Pascal Vivet,
Ivan Miro Panades,
Edith Beigné,
Suzanne Lesecq:
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures.
J. Low Power Electronics 7(3): 328-340 (2011) |
| 11 |  | Bettina Rebaud,
Marc Belleville,
Edith Beigné,
Christian Bernard,
Michel Robert,
Philippe Maurine,
Nadine Azémard:
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectronics Journal 42(5): 718-732 (2011) |
| 2010 |
| 10 |  | Jean-Frédéric Christmann,
Edith Beigné,
Cyril Condemine,
Nicolas Leblond,
Pascal Vivet,
G. Waltisperger,
Jérôme Willemin:
Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems.
ASYNC 2010: 62-71 |
| 9 |  | Pascal Vivet,
Edith Beigné,
Hugo Lebreton,
Nacer-Eddine Zergainoh:
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS.
PATMOS 2010: 94-104 |
| 8 |  | Motoi Ichihashi,
Hélène Lhermet,
Edith Beigné,
Frédéric Rothan,
Marc Belleville,
Amara Amara:
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process.
J. Low Power Electronics 6(1): 201-210 (2010) |
| 2009 |
| 7 |  | Bettina Rebaud,
Marc Belleville,
Edith Beigné,
Christian Bernard,
Michel Robert,
Philippe Maurine,
Nadine Azémard:
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
PATMOS 2009: 266-275 |
| 6 |  | Motoi Ichihashi,
Hélène Lhermet,
Edith Beigné,
Frédéric Rothan,
Marc Belleville,
Amara Amara:
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process.
PATMOS 2009: 336-346 |
| 5 |  | Yvain Thonnart,
Edith Beigné,
Alexandre Valentian,
Pascal Vivet:
Power Reduction of Asynchronous Logic Circuits Using Activity Detection.
IEEE Trans. VLSI Syst. 17(7): 893-906 (2009) |
| 2008 |
| 4 |  | Edith Beigné,
Fabien Clermidy,
Sylvain Miermont,
Pascal Vivet:
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.
NOCS 2008: 129-138 |
| 2006 |
| 3 |  | Edith Beigné,
Pascal Vivet:
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture.
ASYNC 2006: 172-183 |
| 2 |  | D. Caucheteux,
Edith Beigné,
Elisabeth Crochon,
Marc Renaudin:
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.
ASYNC 2006: 86-97 |
| 2005 |
| 1 |  | Edith Beigné,
Fabien Clermidy,
Pascal Vivet,
Alain Clouard,
Marc Renaudin:
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.
ASYNC 2005: 54-63 |