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| 2011 | ||
|---|---|---|
| 5 | Rami Beidas, Wai Sum Mong, Jianwen Zhu: Register pressure aware scheduling for high level synthesis. ASP-DAC 2011: 461-466 | |
| 2010 | ||
| 4 | Alexander Choong, Rami Beidas, Jianwen Zhu: Parallelizing Simulated Annealing-Based Placement Using GPGPU. FPL 2010: 31-34 | |
| 2005 | ||
| 3 | Rami Beidas, Jianwen Zhu: Scalable interprocedural register allocation for high level synthesis. ASP-DAC 2005: 511-516 | |
| 2004 | ||
| 2 | Rami Beidas, Jianwen Zhu: A queuing-theoretic performance model for context-flow system-on-chip platforms. ESTImedia 2004: 21-26 | |
| 2003 | ||
| 1 | Rami Beidas, Jianwen Zhu: Performance Efficiency of Context-Flow System-on-Chip Platform. ICCAD 2003: 356-362 | |
| 1 | Alexander Choong | [4] |
| 2 | Wai Sum Mong | [5] |
| 3 | Jianwen Zhu | [1] [2] [3] [4] [5] |
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