Peter A. Beerel

	2011
66		Arash Saifhashemi, Peter A. Beerel: SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces. CPA 2011: 287-302
65		Pankaj Golani, Peter A. Beerel: An area-efficient multi-level single-track pipeline template. DATE 2011: 1509-1512
64		Georgios D. Dimou, Peter A. Beerel, Andrew Lines: Performance-Driven Clustering of Asynchronous Circuits. PATMOS 2011: 92-101
63		Peter A. Beerel, Georgios D. Dimou, Andrew Lines: Proteus: An ASIC Flow for GHz Asynchronous Designs. IEEE Design & Test of Computers 28(5): 36-51 (2011)
62		Kenneth S. Stevens, Pankaj Golani, Peter A. Beerel: Energy and Performance Models for Synchronous and Asynchronous Communication. IEEE Trans. VLSI Syst. 19(3): 369-382 (2011)
	2010
61		Prasad Joshi, Peter A. Beerel, Marly Roncken, Ivan Sutherland: Timing Verification of GasP Asynchronous Circuits: Predicted Delay Variations Observed by Experiment. Concurrency, Compositionality, and Correctness 2010: 260-276
	2009
60		Ritej Bachhawat, Pankaj Golani, Peter A. Beerel: Crosstalk in High-Performance Asynchronous Designs. PATMOS 2009: 136-145
	2007
59		Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel: Design of a High-Speed Asynchronous Turbo Decoder. ASYNC 2007: 49-59
58		Peter A. Beerel, Marly Roncken: Low Power and Energy Efficient Asynchronous Design. J. Low Power Electronics 3(3): 234-253 (2007)
	2006
57		Sunan Tugsinavisut, Roger Su, Peter A. Beerel: High-level Synthesis for Highly Concurrent Hardware Systems. ACSD 2006: 79-90
56		Peter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies: Slack Matching Asynchronous Designs. ASYNC 2006: 184-194
55		Pankaj Golani, Peter A. Beerel: High-Performance Noise-Robust Asynchronous Circuits. ISVLSI 2006: 173-178
54		Peter A. Beerel: Asynchronous Design for High-Speed and Low-Power Circuits. PATMOS 2006: 669
53		Recep O. Ozdag, Peter A. Beerel: An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates. IEEE Trans. VLSI Syst. 14(9): 975-985 (2006)
52		Sangyun Kim, Peter A. Beerel: Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 389-402 (2006)
51		Pankaj Golani, Peter A. Beerel: Back-Annotation in High-Speed Asynchronous Design. J. Low Power Electronics 2(1): 37-44 (2006)
	2005
50		Arash Saifhashemi, Peter A. Beerel: High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog. CPA 2005: 275-288
49		Pankaj Golani, Peter A. Beerel: Back Annotation in High Speed Asynchronous Design. PATMOS 2005: 227-236
48		Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim, Peter A. Beerel: Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication. IEEE Trans. VLSI Syst. 13(4): 448-461 (2005)
	2004
47		Recep O. Ozdag, Peter A. Beerel: A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates. ASYNC 2004: 187-197
46		Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel: High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. ASYNC 2004: 95-105
45		Peter A. Beerel, Jordi Cortadella, Alex Kondratyev: Bridging the Gap between Asynchronous Design and Designers. VLSI Design 2004: 18-20
	2003
44		Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel: An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. ISCAS (5) 2003: 361-364
43		Joong-Seok Moon, William C. Athas, Sigfrid D. Soli, Jeffrey T. Draper, Peter A. Beerel: Voltage-pulse driven harmonic resonant rail drivers for low-power applications. IEEE Trans. VLSI Syst. 11(5): 762-777 (2003)
	2002
42		Peter A. Beerel, Ken S. Stevens, Hoshik Kim: Relative Timing Based Verification of Timed Circuits and Systems. ASYNC 2002: 115-124
41		Recep O. Ozdag, Peter A. Beerel: High-Speed QDI Asynchronous Pipelines. ASYNC 2002: 13-22
40		Peter A. Beerel, Aiguo Xie: Performance Analysis of Asynchronous Circuits Using Markov Chains. Concurrency and Hardware Design 2002: 313-344
39		Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick: High-Speed Non-Linear Asynchronous Pipelines. DATE 2002: 1000-1007
38		Marcos Ferretti, Peter A. Beerel: Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding. DATE 2002: 1008-1015
37		Sunan Tugsinavisut, Peter A. Beerel: Control Circuit Templates for Asynchronous Bundled-Data Pipelines. DATE 2002: 1098
36		Peter A. Beerel: Asynchronous Circuits: An Increasingly Practical Design Solution (invited). ISQED 2002: 367-372
35		Sangyun Kim, Sunan Tugsinavisut, Peter A. Beerel: Reducing probabilistic timed petri nets for asynchronous architectural analysis. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 140-147
	2001
34		Joong-Seok Moon, William C. Athas, Peter A. Beerel: Theory and practical implementation of harmonic resonant rail driver. ISLPED 2001: 153-158
33		Peter A. Beerel, Keith M. Chugg: A low latency SISO with application to broadband turbo decoding. IEEE Journal on Selected Areas in Communications 19(5): 860-870 (2001)
	2000
32		Sangyun Kim, Peter A. Beerel: Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm. ICCAD 2000: 296-302
31		Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong: An asynchronous matrix-vector multiplier for discrete cosine transform. ISLPED 2000: 256-261
30		Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan: Sibling-substitution-based BDD minimization using don't cares. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 44-55 (2000)
29		Aiguo Xie, Peter A. Beerel: Implicit enumeration of strongly connected components and anapplication to formal verification. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1225-1230 (2000)
	1999
28		Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70
27		Aiguo Xie, Sangyun Kim, Peter A. Beerel: Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice. ASYNC 1999: 94-107
26		Hüsnü Yenigün, Vladimir Levin, Doron Peled, Peter A. Beerel: Hazard-Freedom Checking in Speed-Independent Systems. CHARME 1999: 317-320
25		Youpyo Hong, Peter A. Beerel: Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares. DATE 1999: 13-
24		Aiguo Xie, Peter A. Beerel: Implicit enumeration of strongly connected components. ICCAD 1999: 37-40
23		Peter A. Beerel, Sangyun Kim, Pei-Chuan Yeh, Kyeounsoo Kim: Statistically optimized asynchronous barrel shifters for variable length codecs. ISLPED 1999: 261-263
22		Wei-Chun Chou, Peter A. Beerel, Kenneth Y. Yun: Average-case technology mapping of asynchronous burst-mode circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1418-1434 (1999)
21		Aiguo Xie, Peter A. Beerel: Accelerating Markovian analysis of asynchronous systems using state compression. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 869-888 (1999)
	1998
20		Aiguo Xie, Peter A. Beerel: Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression. ASYNC 1998: 247-
19		Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-
18		Youpyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen Sentovich: Don't Care-Based BDD Minimization for Embedded Software. DAC 1998: 506-509
17		Aiguo Xie, Peter A. Beerel: Efficient State Classification of Finite State Markov Chains. DAC 1998: 605-610
16		Peter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng: Checking Combinational Equivalence of Speed-Independent Circuits. Formal Methods in System Design 13(1): 37-85 (1998)
15		Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, Julio Arceo: The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. IEEE Trans. VLSI Syst. 6(4): 643-655 (1998)
14		Aiguo Xie, Peter A. Beerel: Efficient state classification of finite-state Markov chains. IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1334-1339 (1998)
13		Peter A. Beerel, Chris J. Myers, Teresa H. Y. Meng: Covering conditions and algorithms for the synthesis of speed-independent circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 205-219 (1998)
	1997
12		Kenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Peter A. Beerel, Vida Vakilotojar: The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver. ASYNC 1997: 140-
11		Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel: Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. ASYNC 1997: 210-
10		Aiguo Xie, Peter A. Beerel: Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events. ASYNC 1997: 64-75
9		Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan: Safe BDD Minimization Using Don't Cares. DAC 1997: 208-213
8		Vida Vakilotojar, Peter A. Beerel: RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking. Integration 24(1): 19-35 (1997)
	1996
7		Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar: Estimation of energy consumption in speed-independent control circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 672-680 (1996)
	1995
6		Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng: Technology mapping of timed circuits. ASYNC 1995: 138-
5		Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh: Estimation and bounding of energy consumption in burst-mode control circuits. ICCAD 1995: 26-33
4		Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar: Estimation of energy consumption in speed-independent control circuits. ISLPD 1995: 39-44
	1993
3		Peter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng: Efficient verification of determinate speed-independent circuits. ICCAD 1993: 261-267
	1992
2		Peter A. Beerel, Teresa H. Y. Meng: Automatic gate-level synthesis of speed-independent circuits. ICCAD 1992: 581-586
	1991
1		Peter A. Beerel, Teresa H. Y. Meng: Testability of Asynchronous Timed Control Circuits with Delay Assumptions. DAC 1991: 446-451

Coauthor Index

1	Boris Agapiev	[28]
2	Julio Arceo	[12] [15]
3	William C. Athas	[34] [43]
4	Ritej Bachhawat	[60]
5	Jerry R. Burch	[3] [9] [16] [30]
6	Wei-Chun Chou	[19] [22]
7	Keith M. Chugg	[33]
8	Jordi Cortadella	[45]
9	Mike Davies	[56]
10	Charles Dike	[28]
11	Georgios D. Dimou	[59] [63] [64]
12	Ayoob E. Dooply	[11] [12] [15]
13	Jeffrey T. Draper (Jeff Draper)	[43]
14	Marcos Ferretti	[38] [46]
15	Ran Ginosar	[19] [28]
16	Pankaj Golani	[49] [51] [55] [59] [60] [62] [65]
17	Youpyo Hong	[9] [18] [25] [30] [31] [48]
18	Cheng-Ta Hsieh	[4] [7]
19	Suwicha Jirayucharoensak	[44]
20	Prasad Joshi	[61]
21	Daewook Kim	[48]
22	Hoshik Kim	[42]
23	Kyeounsoo Kim	[23] [31] [48]
24	Nam-Hoon Kim	[56]
25	Sangyun Kim	[23] [27] [32] [35] [52]
26	Rakefet Kol	[19] [28]
27	Alex Kondratyev	[45]
28	Luciano Lavagno	[18]
29	Vladimir Levin	[26]
30	Andrew Lines	[56] [63] [64]
31	Kenneth L. McMillan	[9] [30]
32	Teresa H. Y. Meng	[1] [2] [3] [6] [13] [16]
33	Joong-Seok Moon	[34] [43]
34	Chris J. Myers	[6] [13] [19] [28]
35	Steven M. Nowick	[5] [11] [39]
36	Recep O. Ozdag	[39] [41] [46] [47] [53]
37	Doron Peled	[26]
38	Mallika Prakash	[59]
39	Marly Roncken	[28] [58] [61]
40	Shai Rotem	[19] [28]
41	Arash Saifhashemi	[50] [66]
42	Ellen Sentovich (Ellen M. Sentovich)	[18]
43	Montek Singh	[39]
44	Sigfrid D. Soli	[43]
45	Kenneth S. Stevens (Ken S. Stevens)	[19] [28] [42] [62]
46	Roger Su	[57]
47	Ivan Sutherland	[61]
48	Sunan Tugsinavisut	[35] [37] [44] [48] [57]
49	Vida Vakilotojar	[8] [12] [15]
50	Suhrid A. Wadekar	[4] [7]
51	Aiguo Xie	[10] [14] [17] [20] [21] [24] [27] [29] [40]
52	Pei-Chuan Yeh	[5] [23]
53	Hüsnü Yenigün	[26]
54	Kenneth Y. Yun	[5] [11] [12] [15] [19] [22] [28]

Colors in the list of coauthors

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