Kia Bazargan

	2012
54		Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja: The synthesis of linear Finite State Machine-based Stochastic Computational Elements. ASP-DAC 2012: 757-762
	2011
53		Hossein Omidian Savarbaghi, Kia Bazargan: FPGA placement by graph isomorphism (abstract only). FPGA 2011: 284
52		Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja: An Architecture for Fault-Tolerant Computation with Stochastic Logic. IEEE Trans. Computers 60(1): 93-105 (2011)
	2010
51		Pongstorn Maidee, Kia Bazargan: A fast SPFD-based rewiring technique. ASP-DAC 2010: 55-60
50		Pongstorn Maidee, Kia Bazargan: Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1870-1883 (2010)
	2009
49		Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan: A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC 2009: 1-4
48		Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja: A reconfigurable stochastic architecture for highly reliable computing. ACM Great Lakes Symposium on VLSI 2009: 315-320
47		Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan: Using randomization to cope with circuit uncertainty. DATE 2009: 815-820
46		Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja: The synthesis of combinational logic to generate probabilities. ICCAD 2009: 367-374
45		Satish Sivaswamy, Kia Bazargan, Marc D. Riedel: Estimation and optimization of reliability of noisy digital circuits. ISQED 2009: 213-219
44		Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 350-363 (2009)
	2008
43		Pongstorn Maidee, Nagib Hakim, Kia Bazargan: FPGA family composition and effects of specialized blocks. FPL 2008: 101-106
42		Hushrav Mogal, Kia Bazargan: Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. ICCAD 2008: 302-305
41		Satish Sivaswamy, Kia Bazargan: Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. TRETS 1(1): (2008)
	2007
40		Hushrav Mogal, Kia Bazargan: Microarchitecture floorplanning for sub-threshold leakage reduction. DATE 2007: 1238-1243
39		Satish Sivaswamy, Kia Bazargan: Variation-aware routing for FPGAs. FPGA 2007: 71-79
38		Pongstorn Maidee, Kia Bazargan: A generalized and unified SPFD-based rewiring technique. FPL 2007: 305-310
37		Satish Sivaswamy, Kia Bazargan: Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. FPL 2007: 429-434
36		Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Clustering based pruning for statistical criticality computation under process variations. ICCAD 2007: 340-343
35		Kia Bazargan, André DeHon: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 201-202 (2007)
	2006
34		Pongstorn Maidee, Kia Bazargan: Defect-Tolerant FPGA Architecture Exploration. FPL 2006: 1-6
33		Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh: Statistical Analysis and Design of HARP FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2088-2102 (2006)
32		Cristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1132-1140 (2006)
31		Cristinel Ababei, Kia Bazargan: Non-contiguous linear placement for reconfigurable fabrics. IJES 2(1/2): 86-94 (2006)
	2005
30		Cristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. ASP-DAC 2005: 773-778
29		Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh: HARP: hard-wired routing pattern FPGAs. FPGA 2005: 21-29
28		Cristinel Ababei, Hushrav Mogal, Kia Bazargan: 3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA 2005: 263
27		Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar: Placement and Routing in 3D Integrated Circuits. IEEE Design & Test of Computers 22(6): 520-531 (2005)
26		Pongstorn Maidee, Cristinel Ababei, Kia Bazargan: Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 395-406 (2005)
25		Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan: A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. J. Comput. Sci. Technol. 20(5): 596-606 (2005)
	2004
24		Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan: Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory. Asia-Pacific Computer Systems Architecture Conference 2004: 88-101
23		Cristinel Ababei, Pongstorn Maidee, Kia Bazargan: Exploring Potential Benefits of 3D FPGA Integration. FPL 2004: 874-880
22		Cristinel Ababei, Kia Bazargan: Non-Contiguous Linear Placement for Reconfigurable Fabrics. IPDPS 2004
21		John Lach, Kia Bazargan: Editorial: Special issue on dynamically adaptable embedded systems. ACM Trans. Embedded Comput. Syst. 3(2): 233-236 (2004)
	2003
20		Pongstorn Maidee, Cristinel Ababei, Kia Bazargan: Fast timing-driven partitioning-based placement for island style FPGAs. DAC 2003: 598-603
19		Wonjoon Choi, Kia Bazargan: Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. DATE 2003: 11104-11105
18		Karthikeyan Bhasyam, Kia Bazargan: HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. DSD 2003: 264-271
17		Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan: Linear Placement for Static / Dynamic Reconfiguration in JBits. FCCM 2003: 300-301
16		Wonjoon Choi, Kia Bazargan: Incremental Placement for Timing Optimization. ICCAD 2003: 463-466
15		Cristinel Ababei, Kia Bazargan: Placement Method Targeting Predictability Robustness and Performance. ICCAD 2003: 81-85
14		Cristinel Ababei, Kia Bazargan: Timing Minimization by Statistical Timing hMetis-based Partitioning. VLSI Design 2003: 58-63
	2002
13		Jinghuan Chen, Jaekyun Moon, Kia Bazargan: A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. DAC 2002: 349-354
12		Cristinel Ababei, Kia Bazargan: Statistical Timing Driven Partitioning for VLSI Circuits. DATE 2002: 1109
11		Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis: Multi-objective circuit partitioning for cutsize and path-based delay minimization. ICCAD 2002: 181-185
	2001
10		Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh: Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. DAC 2001: 635-640
9		Abhishek Ranjan, Kia Bazargan, S. Ogrenci, Majid Sarrafzadeh: Fast floorplanning for effective prediction and construction. IEEE Trans. VLSI Syst. 9(2): 341-351 (2001)
	2000
8		Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh: Fast and accurate estimation of floorplans in logic/high-level synthesis. ACM Great Lakes Symposium on VLSI 2000: 95-100
7		Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh: A C to Hardware/Software Compiler. FCCM 2000: 331-332
6		Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh: Fast Hierarchical Floorplanning with Congestion and Timing Control. ICCD 2000: 357-362
5		Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. Design Autom. for Emb. Sys. 5(3-4): 329-338 (2000)
4		Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: Fast Template Placement for Reconfigurable Computing Systems. IEEE Design & Test of Computers 17(1): 68-83 (2000)
	1999
3		Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh: 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. IEEE International Workshop on Rapid System Prototyping 1999: 38-
2		Kia Bazargan, Samjung Kim, Majid Sarrafzadeh: Nostradamus: a floorplanner of uncertain designs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 389-397 (1999)
	1998
1		Kia Bazargan, Samjung Kim, Majid Sarrafzadeh: Nostradamus: a floorplanner of uncertain design. ISPD 1998: 18-23

Coauthor Index

1	Cristinel Ababei	[11] [12] [14] [15] [20] [22] [23] [26] [27] [28] [29] [30] [31] [32] [33]
2	Ehsan K. Ardestani	[47]
3	Karthikeyan Bhasyam	[18]
4	Elaheh Bozorgzadeh (Eli Bozorgzadeh)	[29] [33]
5	Jinghuan Chen	[13]
6	Ying Chen	[24] [25]
7	Wonjoon Choi	[16] [19]
8	André DeHon	[35]
9	Yan Feng	[27]
10	Brent Goplen	[27]
11	Nagib Hakim	[43]
12	George Karypis	[11]
13	Ryan Kastner	[3] [4] [5] [7] [29] [33]
14	Samjung Kim	[1] [2]
15	John Lach	[21]
16	Peng Li	[54]
17	Xin Li	[48] [52]
18	David J. Lilja	[24] [25] [46] [48] [52] [54]
19	Pongstorn Maidee	[20] [23] [26] [34] [38] [43] [50] [51]
20	Vamsi Krishna Marreddy	[17]
21	Seda Ogrenci Memik (Seda Ogrenci)	[7] [10]
22	Hushrav Mogal	[27] [28] [30] [32] [36] [40] [42] [44]
23	Jaekyun Moon	[13]
24	Sharareh Noorbaloochi	[17]
25	S. Ogrenci	[9]
26	Vasudev V. Pai	[24] [25]
27	Haifeng Qian	[36] [44]
28	Weikang Qian	[46] [48] [52] [54]
29	Karthik Ranganathan	[24] [25]
30	Abhishek Ranjan	[6] [8] [9]
31	Seyyed Ahmad Razavi	[49]
32	Marc D. Riedel	[45] [46] [48] [52] [54]
33	Hamid Safizadeh	[47]
34	Sachin S. Sapatnekar	[27] [36] [44]
35	Majid Sarrafzadeh	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
36	Hossein Omidian Savarbaghi	[53]
37	Navaratnasothie Selvakkumaran	[11]
38	Satish Sivaswamy	[29] [33] [37] [39] [41] [45]
39	Mohammad Tahghighi	[47]
40	Gholamhossein Tavasoli	[47]
41	Gang Wang	[29] [33]
42	Morteza Saheb Zamani	[49]
43	Tianpei Zhang	[27]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page