 | 2010 |
| 13 |  | Pouria Bastani,
Nicholas Callegari,
Li-C. Wang,
Magdy S. Abadir:
Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch.
IEEE Design & Test of Computers 27(3): 42-53 (2010) |
| 2009 |
| 12 |  | Nicholas Callegari,
Pouria Bastani,
Li-C. Wang,
Sreejit Chakravarty,
Alexander Tetelbaum:
Path selection for monitoring unexpected systematic timing effects.
ASP-DAC 2009: 781-786 |
| 11 |  | Nicholas Callegari,
Li-C. Wang,
Pouria Bastani:
Speedpath analysis based on hypothesis pruning and ranking.
DAC 2009: 346-351 |
| 10 |  | Nicholas Callegari,
Li-C. Wang,
Pouria Bastani:
Feature based similarity search with application to speedpath analysis.
ITC 2009: 1-10 |
| 9 |  | Nicholas Callegari,
Pouria Bastani,
Li-C. Wang,
Magdy S. Abadir:
A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1728-1741 (2009) |
| 2008 |
| 8 |  | Pouria Bastani,
Kip Killpack,
Li-C. Wang,
Eli Chiprout:
Speedpath prediction based on learning from a small set of examples.
DAC 2008: 217-222 |
| 7 |  | Pouria Bastani,
Nicholas Callegari,
Li-C. Wang,
Magdy S. Abadir:
Statistical diagnosis of unmodeled systematic timing effects.
DAC 2008: 355-360 |
| 6 |  | Chandramouli V. Kashyap,
Pouria Bastani,
Kip Killpack,
Chirayu S. Amin:
Silicon feedback to improve frequency of high-performance microprocessors: an overview.
ICCAD 2008: 778-782 |
| 5 |  | Pouria Bastani,
Nicholas Callegari,
Li-C. Wang,
Magdy S. Abadir:
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained.
ITC 2008: 1-10 |
| 4 |  | Kip Killpack,
Suriyaprakash Natarajan,
Arun Krishnamachary,
Pouria Bastani:
Case Study on Speed Failure Causes in a Microprocessor.
IEEE Design & Test of Computers 25(3): 224-230 (2008) |
| 3 |  | Pouria Bastani,
Li-C. Wang,
Magdy S. Abadir:
Linking Statistical Learning to Diagnosis.
IEEE Design & Test of Computers 25(3): 232-239 (2008) |
| 2007 |
| 2 |  | Li-C. Wang,
Pouria Bastani,
Magdy S. Abadir:
Design-Silicon Timing Correlation A Data Mining Perspective.
DAC 2007: 384-389 |
| 1 |  | Pouria Bastani,
Benjamin N. Lee,
Li-C. Wang,
Savithri Sundareswaran,
Magdy S. Abadir:
Analyzing the risk of timing modeling based on path delay tests.
ITC 2007: 1-10 |