 | 2011 |
| 11 |  | Lina Sawalha,
Sonya Wolff,
Monte P. Tull,
Ronald D. Barnes:
Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors.
DSD 2011: 736-745 |
| 10 |  | Ekasit Vorakitolan,
Joseph P. Havlicek,
Mohammed Atiquzzaman,
Ronald D. Barnes:
Exploiting trunked radio to support ITS network expansion and redundancy.
PIMRC 2011: 761-766 |
| 9 |  | Lina Sawalha,
Monte P. Tull,
Ronald D. Barnes:
Thread scheduling for heterogeneous multicore processors using phase identification.
SIGMETRICS Performance Evaluation Review 39(3): 125-127 (2011) |
| 2006 |
| 8 |  | Ronald D. Barnes,
Shane Ryoo,
Wen-mei W. Hwu:
Tolerating Cache-Miss Latency with Multipass Pipelines.
IEEE Micro 26(1): 40-47 (2006) |
| 7 |  | Ronald D. Barnes,
John W. Sias,
Erik M. Nystrom,
Sanjay J. Patel,
Jose (Nacho) Navarro,
Wen-mei W. Hwu:
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining.
IEEE Trans. Computers 55(1): 18-33 (2006) |
| 2005 |
| 6 |  | Ronald D. Barnes,
Shane Ryoo,
Wen-mei W. Hwu:
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense.
MICRO 2005: 319-330 |
| 2003 |
| 5 |  | Ronald D. Barnes,
Erik M. Nystrom,
John W. Sias,
Sanjay J. Patel,
Nacho Navarro,
Wen-mei W. Hwu:
Beating in-order stalls with "flea-flicker" two-pass pipelining.
MICRO 2003: 387-398 |
| 2002 |
| 4 |  | Ronald D. Barnes,
Erik M. Nystrom,
Matthew C. Merten,
Wen-mei W. Hwu:
Vacuum packing: extracting hardware-detected program phases for post-link optimization.
MICRO 2002: 233-244 |
| 2001 |
| 3 |  | Erik M. Nystrom,
Ronald D. Barnes,
Matthew C. Merten,
Wen-mei W. Hwu:
Code Reordering and Speculation Support for Dynamic Optimization System.
IEEE PACT 2001: 163-174 |
| 2 |  | Matthew C. Merten,
Andrew R. Trick,
Ronald D. Barnes,
Erik M. Nystrom,
Christopher N. George,
John C. Gyllenhaal,
Wen-mei W. Hwu:
An Architectural Framework for Runtime Optimization.
IEEE Trans. Computers 50(6): 567-589 (2001) |
| 2000 |
| 1 |  | Matthew C. Merten,
Andrew R. Trick,
Erik M. Nystrom,
Ronald D. Barnes,
Wen-mei W. Hwu:
A hardware mechanism for dynamic extraction and relayout of program hot spots.
ISCA 2000: 59-70 |