Erich Barke

	2011
63		Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz: A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD 2011: 708-715
62		Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke: Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation. ICCD 2011: 108-112
61		Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz: A gate sizing method for glitch power reduction. SoCC 2011: 24-29
60		M. Zhang, R. Haussler, Markus Olbrich, Harald Kinzelbach, Erich Barke: A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. VLSI Design 2011: 106-111
	2010
59		Florian Schupfer, Christoph Grimm, Markus Olbrich, Michael Kärgel, Erich Barke: Towards Abstract Analysis Techniques for Range Based System Simulations. FDL 2010: 159-164
58		Daniel Zaum, Stefan Hoelldampf, Markus Olbrich, Erich Barke, Ingmar Neumann: An Accelerated Mixed-Signal Simulation Kernel for SystemC. FDL 2010: 234-239
	2009
57		Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Yifan Wang: Formal approaches to analog circuit verification. DATE 2009: 724-729
56		Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler: Fast dynamic power estimation considering glitch filtering. SoCC 2009: 361-364
	2008
55		Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl: Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22
54		Markus Olbrich, Erich Barke: Distribution arithmetic for stochastical analysis. ASP-DAC 2008: 537-542
53		Darius Grabowski, Markus Olbrich, Erich Barke: Analog circuit simulation using range arithmetics. ASP-DAC 2008: 762-767
52		Peter Leppelt, Erich Barke: Determining the Technical Complexity of Integrated Circuits. DATE 2008: 935
51		Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke: A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles. DDECS 2008: 54-58
50		Stefan Hoelldampf, Daniel Zaum, Markus Olbrich, Erich Barke, Ingmar Neumann, Sebastian Schmidt: Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited). FDL 2008: 73-77
	2007
49		Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl: Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48
48		Hedi Harizi, Robert HauBler, Markus Olbrich, Erich Barke: Efficient Modeling Techniques for Dynamic Voltage Drop Analysis. DAC 2007: 706-711
47		M. Zhang, Markus Olbrich, D. Seider, M. Frerichs, Harald Kinzelbach, Erich Barke: CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions. DATE 2007: 243-248
46		Darius Grabowski, Markus Olbrich, Christoph Grimm, Erich Barke: Range Arithmetics to Speed up Reachability Analysis of Analog Systems. FDL 2007: 38-43
45		Jan Torben Weinkopf, Klaus Harbich, Erich Barke: Incremental Fault Emulation. FPL 2007: 542-545
44		Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten: Algorithms for automatic length compensation of busses in analog integrated circuits. ISPD 2007: 159-166
	2006
43		Daniel Platte, S. Jing, R. Sommer, Erich Barke: Using Sequential Equations to Improve Efficiency and Robustness. FDL 2006: 83-90
42		Jan Torben Weinkopf, Klaus Harbich, Erich Barke: Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. FPL 2006: 1-6
41		Darius Grabowski, Christoph Grimm, Erich Barke: Semi-symbolic modeling and simulation of circuits and systems. ISCAS 2006
40		Darius Grabowski, Daniel Platte, Lars Hedrich, Erich Barke: Time Constrained Verification of Analog Circuits using Model-Checking Algorithms. Electr. Notes Theor. Comput. Sci. 153(3): 37-52 (2006)
	2005
39		Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten: Routing of analog busses with parasitic symmetry. ISPD 2005: 14-19
	2004
38		Markus Olbrich, Erich Barke: Placement Using a Localization Probability Model (LPM). DATE 2004: 1412
37		Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. DATE 2004: 442-447
36		Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke: Wirelength Reduction Using 3-D Physical Design. PATMOS 2004: 453-462
	2003
35		Andreas Hermann, Markus Olbrich, Erich Barke: Substrate Modeling and Noise Reduction in Mixed-Signal Circuits. VLSI-SOC 2003: 13-18
	2002
34		Walter Hartong, Lars Hedrich, Erich Barke: On Discrete Modeling and Model Checking for Nonlinear Analog Systems. CAV 2002: 401-413
33		Walter Hartong, Lars Hedrich, Erich Barke: Model checking algorithms for analog verification. DAC 2002: 542-547
32		Walter Hartong, Lars Hedrich, Erich Barke: An Approach to Model Checking for Nonlinear Analog Systems. DATE 2002: 1080
31		Joerg Abke, Erich Barke: A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . DATE 2002: 1085
30		Ralf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke: Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. DATE 2002: 274-278
29		Andreas C. Lemke, Lars Hedrich, Erich Barke: Analog circuit sizing based on formal methods using affine arithmetic. ICCAD 2002: 486-489
28		Silke Salewski, Erich Barke: An Upper Bound for 3D Slicing Floorplans. VLSI Design 2002: 567-572
	2001
27		Joachim Küter, Erich Barke: Architecture driven partitioning. DATE 2001: 479-487
26		Markus Olbrich, Achim Rein, Erich Barke: An improved hierarchical classification algorithm for structural analysis of integrated circuits. DATE 2001: 807
25		Klaus Harbich, Erich Barke: PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. FPL 2001: 133-141
24		Joerg Abke, Erich Barke: A New Placement Method for Direct Mapping into LUT-Based FPGAs. FPL 2001: 27-36
23		Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch: CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE 2001: 71-72
	2000
22		Dimitrios Soudris, Peter Pirsch, Erich Barke: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings Springer 2000
21		Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke: A current driven routing and verification methodology for analog applications. DAC 2000: 385-389
20		Thorsten Adler, Erich Barke: Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. DATE 2000: 446-450
19		Matthias Ringe, Thomas Lindenkreuz, Erich Barke: Static Timing Analysis Taking Crosstalk into Account. DATE 2000: 451-455
18		Joerg Abke, Erich Barke: CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs. FPL 2000: 191-200
17		Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel: PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. PATMOS 2000: 306-315
	1999
16		Klaus Harbich, Jörn Stohmann, Erich Barke, Ludwig Schwoerer: A Case Study: Logic Emulation - Pitfalls and Solutions. IEEE International Workshop on Rapid System Prototyping 1999: 160-
15		Joerg Abke, Erich Barke, Jörn Stohmann: A Universal Module Generator for LUT-Based FPGAs. IEEE International Workshop on Rapid System Prototyping 1999: 230-235
	1998
14		Reza Sedaghat-Maman, Erich Barke: Real Time Fault Injection Using Logic Emulators. ASP-DAC 1998: 475-479
13		Lars Hedrich, Erich Barke: A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. DATE 1998: 649-654
12		Matthias Ringe, Thomas Lindenkreuz, Erich Barke: Path Verification Using Boolean Satisfiability. DATE 1998: 965-966
11		Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke: An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping. FPL 1998: 79-88
	1997
10		Jörn Stohmann, Erich Barke: A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. ICCD 1997: 489-495
	1996
9		Carsten Borchers, Lars Hedrich, Erich Barke: Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits. DAC 1996: 236-239
8		Jörn Stohmann, Erich Barke: A Universal CLA Adder Generator for SRAM-Based FPGAs. FPL 1996: 44-54
7		Dirk Behrens, Klaus Harbich, Erich Barke: Hierarchical partitioning. ICCAD 1996: 470-477
	1995
6		Lars Hedrich, Erich Barke: A formal approach to nonlinear analog circuit verification. ICCAD 1995: 123-127
	1988
5		Erich Barke: Line-to-ground capacitance calculation for VLSI: a comparison. IEEE Trans. on CAD of Integrated Circuits and Systems 7(2): 295-298 (1988)
	1985
4		Erich Barke: Resistance calculation from mask artwork data by finite element method. DAC 1985: 305-311
3		Erich Barke: FERKEL: Technologieunabhängiges direktivengesteuertes Programmsystem zur Entwurfsregelnprüfung. Angewandte Informatik 27(8): 328-333 (1985)
	1984
2		F. Luellau, T. Hoepken, Erich Barke: A technology independent block extraction algorithm. DAC 1984: 610-615
	1983
1		Erich Barke: A layout verification system for analog bipolar integrated circuits. DAC 1983: 353-359

Coauthor Index

1	Joerg Abke	[15] [18] [24] [31]
2	Thorsten Adler	[20] [21]
3	Dirk Behrens	[7]
4	Volker Meyer zu Bexten	[39] [44]
5	Carsten Borchers	[9]
6	Hiltrud Brocke	[21]
7	Thomas Büchner	[56] [61] [63]
8	Markus Bühler	[55] [56] [61] [63]
9	Volodymyr Burkhay	[37]
10	M. Frerichs	[47]
11	Darius Grabowski	[40] [41] [46] [53] [57]
12	Helmut Graeb	[57]
13	Christoph Grimm	[41] [46] [59]
14	Klaus Harbich	[7] [11] [16] [25] [42] [45]
15	Hedi Harizi	[48]
16	Walter Hartong	[32] [33] [34]
17	Robert HauBler	[48]
18	R. Haussler	[60]
19	Lars Hedrich	[6] [9] [13] [21] [29] [30] [32] [33] [34] [37] [40] [57]
20	Stefan Heinen	[57]
21	Andreas Hermann	[35]
22	Andreas Herrmann	[17]
23	Stefan Hoelldampf	[50] [58] [62]
24	T. Hoepken	[2]
25	Thomas Jambor	[51]
26	S. Jing	[43]
27	Michael Kärgel	[59]
28	Idris Kaya	[36]
29	Harald Kinzelbach	[47] [60]
30	Jürgen Koehl	[49] [55]
31	Mark Bernd Kulaczewski	[23]
32	Joachim Küter	[27]
33	Andreas C. Lemke	[29]
34	Peter Leppelt	[52]
35	Thomas Lindenkreuz	[12] [19]
36	F. Luellau	[2]
37	Lutz Näthke	[37]
38	Ingmar Neumann	[50] [58]
39	Joerg Oehmen	[30]
40	Markus Olbrich	[11] [26] [35] [36] [38] [39] [46] [47] [48] [49] [50] [51] [53] [54] [55] [56] [58] [59] [60] [61] [62] [63]
41	Philipp V. Panitz	[49] [55] [61] [63]
42	Peter Pirsch	[22] [23]
43	Daniel Platte	[40] [43]
44	Ralf Popp	[30] [57]
45	Achim Rein	[26]
46	Matthias Ringe	[12] [19]
47	Silke Salewski	[28] [36]
48	Jürgen Schlöffel	[17]
49	Sebastian Schmidt	[50]
50	Lars A. Schreiner	[39] [44]
51	Florian Schupfer	[59]
52	Ludwig Schwoerer	[16]
53	Reza Sedaghat-Maman	[14]
54	D. Seider	[47]
55	Mathias Silvant	[17]
56	Matthew A. Smith	[44]
57	R. Sommer	[43]
58	Dimitrios Soudris (D. J. Soudris)	[22]
59	Sebastian Steinhorst	[57]
60	Jörn Stohmann	[8] [10] [11] [15] [16]
61	Lei Wang	[56] [61] [63]
62	Yifan Wang	[57]
63	Jan Torben Weinkopf	[42] [45]
64	Daniel Zaum	[50] [51] [58] [62]
65	M. Zhang	[47] [60]
66	Stefan Zimmerman	[23]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page