S. Bapat

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1993

2 S. Bapat, James P. Cohoon: A Parallel VLSI Circuit Layout Methodology. VLSI Design 1993: 236-241

1986

1 S. Bapat, G. Venkatesh: Reasoning about digital systems using temporal logic. DAC 1986: 215-219

	1993
2		S. Bapat, James P. Cohoon: A Parallel VLSI Circuit Layout Methodology. VLSI Design 1993: 236-241
	1986
1		S. Bapat, G. Venkatesh: Reasoning about digital systems using temporal logic. DAC 1986: 215-219

Coauthor Index

1 James P. Cohoon [2]

2 G. Venkatesh [1]

Colors in the list of coauthors

Last update Sun May 27 04:04:01 2012 CET by the DBLP Team —

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