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Aditya Bansal Coauthor index pubzone.org

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DBLP keys2012
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAmith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N. Singh, Aditya Bansal: DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM. ISQED 2012: 470-476
2009
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das: Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD 2009: 631-636
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang: Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectronics Reliability 49(6): 642-649 (2009)
2008
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang: Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ICCD 2008: 457-462
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy: An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. JETC 4(3): (2008)
2007
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy: High Performance and Low Power Electronics on Flexible Substrate. DAC 2007: 274-275
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2059-2068 (2007)
2006
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy: Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC 2006: 237-242
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy: A high density, carbon nanotube capacitor for decoupling applications. DAC 2006: 935-938
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLQikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE 2006: 983-988
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD 2006: 583-586
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Bipul Chandra Paul, Kaushik Roy: An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006)
2005
3no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya Bansal, Kaushik Roy: Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) 2005: 1-4
2004
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHari Ananthan, Aditya Bansal, Kaushik Roy: FinFET SRAM - Device and Circuit Design Considerations. ISQED 2004: 511-516

Coauthor Index

1Emrah Acar [16] [17]
2Hari Ananthan [1] [3] [5]
3Mark M. Budnik [8]
4Tamer Cakici [3] [5]
5Qikai Chen [7]
6Jung Hwan Choi [6] [9] [10]
7Ching-Te Chuang [13] [14] [15] [16]
8Koushik K. Das [16]
9Swaroop Ghosh [12]
10Geng Han [14]
11Fook-Luen Heng [14] [16]
12Kunhyuk Kang [11]
13Rouwaida Kanj [16]
14Jae-Joon Kim [13] [15]
15Keunwoo Kim [13] [16]
16Jin-Fuw Lee [16]
17Jing Li [11] [12]
18Hamid Mahmoodi (Hamid Mahmoodi-Meimand) [3] [5]
19Mesut Meterelliyoz [6] [9] [10]
20Saibal Mukhopadhyay [3] [5] [7] [13] [14] [16]
21Jayathi Murthy [6] [9] [10]
22Sani R. Nassif [16]
23Bipul Chandra Paul (Bipul C. Paul) [4]
24Rahul M. Rao [15]
25Arijit Raychowdhury [8]
26Kaushik Roy [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
27Rama N. Singh [14] [16] [17]
28Siddharth Singh [9]
29Amith Singhee [16] [17]
30James H. Stathis [15]
31Mohammad Imran Younus [17]
32Sufi Zafar [15]

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